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ds07-13701-7e fujitsu semiconductor data sheet 16-bit proprietary microcontroller cmos f 2 mc-16lx mb90570 series mb90573/574/574c/f574/f574a/v570/v570a n description the mb90570 series is a general-purpose 16-bit microcontroller developed and designed by fujitsu for process control applications in consumer products that require high-speed real time processing. it contains an i 2 c* 2 bus interface that allows inter-equipment communication to be implemented readily. this product is well adapted to car audio equipment, vtr systems, and other equipment and systems. the instruction set of f 2 mc-16lx cpu core inherits at architecture of f 2 mc* 1 family with additional instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions, and enhanced bit manipulation instructions. the microcontroller has a 32-bit accumulator for processing long word data. the mb90570 series has peripheral resources of an 8/10-bit a/d converter, an 8-bit d/a converter, uart (sci), an extended i/o serial interface, an 8/16-bit up/down counter/timer, an 8/16-bit ppg timer, i/o timer (a 16-bit free run timer, an input capture (icu), an output compare (ocu)). *1: f 2 mc stands for fujitsu flexible microcontroller. *2: purchase of fujitsu i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. n pac k ag e () 120-pin plastic lqfp (fpt-120p-m05) (fpt-120p-m13) 120-pin plastic qfp 120-pin plastic lqfp (fpt-120p-m21)
2 mb90570 series n features ?clock embedded pll clock multiplication circuit operating clock (pll clock) can be selected from 1/2 to 4 oscillation (at oscillation of 4 mhz, 4 mhz to 16 mhz). minimum instruction execution time: 62.5 ns (at oscillation of 4 mhz, 4 pll clock, operation at v cc of 5.0 v) ? maximum memory space 16 mbytes ? instruction set optimized for controller applications rich data types (bit, byte, word, long word) rich addressing mode (23 types) enhanced signed multiplication/division instruction and reti instruction functions enhanced precision calculation realized by the 32-bit accumulator ? instruction set designed for high level language (c) and multi-task operations adoption of system stack pointer enhanced pointer indirect instructions barrel shift instructions ? program patch function (for two address pointers) ? enhanced execution speed 4-byte instruction queue ? enhanced interrupt function 8 levels, 34 factors ? automatic data transmission function independent of cpu operation extended intelligent i/o service function (ei 2 os): up to 16 channels ? embedded rom size and types mask rom: 128 kbytes/256 kbytes flash rom: 256 kbytes embedded ram size: 6 kbytes/10 kbytes (mask rom) 10 kbytes (flash memory) 10 kbytes (evaluation device) ? low-power consumption (standby) mode sleep mode (mode in which cpu operating clock is stopped) stop mode (mode in which oscillation is stopped) cpu intermittent operation mode hardware standby mode ?process cmos technology ? i/o port general-purpose i/o ports (cmos): 63 ports general-purpose i/o ports (with pull-up resistors): 24 ports general-purpose i/o ports (open-drain): 10 ports total: 97 ports (continued)
3 mb90570 series (continued) ?timer timebase timer/watchdog timer: 1 channel 8/16-bit ppg timer: 8-bit 2 channels or 16-bit 1 channel ? 8/16-bit up/down counter/timer: 1 channel (8-bit 2 channels) ? 16-bit i/o timer 16-bit free run timer: 1 channel input capture (icu): generates an interrupt request by latching a 16-bit free run timer counter value upon detection of an edge input to the pin. output compare (ocu): generates an interrupt request and reverse the output level upon detection of a match between the 16-bit free run timer counter value and the compare setting value. ? extended i/o serial interface: 3 channels ?i 2 c interface (1 channel) serial i/o port for supporting inter ic bus ? uart0 (sci), uart1 (sci) with full-duplex double buffer clock asynchronized or clock synchronized transmission can be selectively used. ? dtp/external interrupt circuit (8 channels) a module for starting extended intelligent i/o service (ei 2 os) and generating an external interrupt triggered by an external input. ? delayed interrupt generation module generates an interrupt request for switching tasks. ? 8/10-bit a/d converter (8 channels) 8/10-bit resolution starting by an external trigger input. conversion time: 26.3 m s ? 8-bit d/a converter (based on the r-2r system) 8-bit resolution: 2 channels (independent) setup time: 12.5 m s ? clock timer: 1 channel ? chip select output (8 channels) an active level can be set. ? clock output function
4 mb90570 series n product lineup (continued) mb90574/c mb90f574/a mb90v570/a classification mask rom products flash rom products evaluation product rom size 128 kbytes 256 kbytes none ram size 6 kbytes 10 kbytes cpu functions the number of instructions: 340 instruction bit length: 8 bits, 16 bits instruction length: 1 byte to 7 bytes data bit length: 1 bit, 8 bits, 16 bits minimum execution time: 62.5 ns (at machine clock of 16 mhz) interrupt processing time: 1.5 m s (at machine clock of 16 mhz, minimum value) ports general-purpose i/o ports (cmos output): 63 general-purpose i/o ports (with pull-up resistor): 24 general-purpose i/o ports (n-ch open-drain output): 10 total: 97 uart0 (sci), uart1 (sci) clock synchronized transmission (62.5 kbps to 1 mbps) clock asynchronized transmission (1202 bps to 9615 bps) transmission can be performed by bi-directional serial transmission or by master/slave connection. 8/10-bit a/d converter resolution: 8/10-bit number of inputs: 8 one-shot conversion mode (converts selected channel only once) scan conversion mode (converts two or more successive channels and can program up to 8 channels.) continuous conversion mode (converts selected channel continuously) stop conversion mode (converts selected channel and stop operation repeatedly) 8/16-bit ppg timer number of channels: 1 (or 8-bit 2 channels) ppg operation of 8-bit or 16-bit a pulse wave of given intervals and given duty ratios can be output. pulse interval: 62.5 ns to 1 m s (at oscillation of 4 mhz, machine clock of 16 mhz) 8/16-bit up/down counter/ timer number of channels: 1 (or 8-bit 2 channels) event input: 6 channels 8-bit up/down counter/timer used: 2 channels 8-bit re-load/compare function supported: 1 channel 16-bit i/o timer 16-bit free run timer number of channel: 1 overflow interrupts output compare (ocu) number of channels: 4 pin input factor: a match signal of compare register input capture (icu) number of channels: 2 rewriting a register value upon a pin input (rising, falling, or both edges) mb90573 item part number
5 mb90570 series (continued) * : varies with conditions such as the operating frequency. (see section n electrical characteristics.) assurance for the mb90v570/a is given only for operation with a tool at a power voltage of 4.5 v to 5.5 v, an operating temperature of 0 to +25 c, and an operating frequency of 1 mhz to 16 mhz. n package and corresponding products : available : not available note: for more information about each package, see section n package dimensions. mb90574/c mb90f574/a mb90v570/a dtp/external interrupt circuit number of inputs: 8 started by a rising edge, a falling edge, an h level input, or an l level input. external interrupt circuit or extended intelligent i/o service (ei 2 os) can be used. delayed interrupt generation module an interrupt generation module for switching tasks used in real time operating systems. extended i/o serial interface clock synchronized transmission (3125 bps to 1 mbps) lsb first/msb first i 2 c interface serial i/o port for supporting inter ic bus timebase timer 18-bit counter interrupt interval: 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms (at oscillation of 4 mhz) 8-bit d/a converter 8-bit resolution number of channels: 2 channels based on the r-2r system watchdog timer reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (at oscillation of 4 mhz, minimum value) low-power consumption (standby) mode sleep/stop/cpu intermittent operation/clock timer/hardware standby process cmos power supply voltage for operation* 4.5 v to 5.5 v package mb90573 mb90574 mb90f574/a MB90574C fpt-120p-m05 fpt-120p-m13 fpt-120p-m21 mb90573 item part number
6 mb90570 series n differences among products memory size in evaluation with an evaluation product, note the difference between the evaluation product and the product actually used. the following items must be taken into consideration. ? the mb90v570/a does not have an internal rom, however, operations equivalent to chips with an internal rom can be evaluated by using a dedicated development tool, enabling selection of rom size by settings of the development tool. ? in the mb90v570/a, images from ff4000 h to ffffff h are mapped to bank 00, and fe0000 h to ff3fff h to mapped to bank fe and ff only. (this setting can be changed by configuring the development tool.) ? in the mb90f574/574/573/f574a/574c, images from ff4000 h to ffffff h are mapped to bank 00, and ff0000 h to ff3fff h to bank ff only. ? the products designated with /a or /c are different from those without /a or /c in that they are dtp/externally- interrupted types which return from standby mode at the ch.0 to ch.1 edge request.
7 mb90570 series n pin assignment p30/ale v ss p27/a23 p26/a22 p25/a21 p24/a20 p23/a19 p22/a18 p21/a17 p20/a16 p17/ad15 p16/ad14 p15/ad13 p14/ad12 p13/ad11 p12/ad10 p11/ad09 p10/ad08 p07/ad07 p06/ad06 p05/ad05 p04/ad04 p03/ad03 p02/ad02 p01/ad01 p00/ad00 v cc x1 x0 v ss p66/out2 p67/out3 v ss c p70 p71 p72 dv cc dv ss p73/da0 p74/da1 av cc avrh avrl av ss p80/an0 p81/an1 p82/an2 p83/an3 p84/an4 p85/an5 p86/an6 p87/an7 v cc p90/cs0 p91/cs1 p92/cs2 p93/cs3 p94/cs4 p95/cs5 (top view) (fpt-120p-m05) (fpt-120p-m13) (fpt-120p-m21) 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 p31/rd p32/wrl p33/wrh p34/hrq p35/hak p36/rdy p37/clk v cc p40/sin0 p41/sot0 p42/sck0 p43/sin1 p44/sot1 p45/sck1 p46/ppg0 p47/ppg1 p50/sin2 p51/sot2 p52/sck2 p53/sin3 p54/sot3 p55/sck3 p56/in0 p57/in1 p60/sin4 p61/sot4 p62/sck4 p63/ckot p64/out0 p65/out1 rst md0 md1 md2 hst pc3 pc2 pc1 pc0 pb7 pb6/adtg pb5/irq5 pb4/irq4 pb3/irq3 pb2/irq2 pb1/irq1 x0a x1a pb0/irq0 pa7/scl pa6/sda pa5/zin1 pa4/bin1 pa3/ain1/irq7 pa2/zin0 pa1/bin0 pa0/ain0/irq6 v ss p97/cs7 p96/cs6
8 mb90570 series n pin description pin no. pin name circuit type function lqfp-120 * 1 qfp-120 * 2 92,93 x0,x1 a high speed oscillator input pins 74,73 x0a,x1a b low speed oscillator input pins 89 to 87 md0 to md2 c these are input pins used to designate the operating mode. they should be connected directly to vcc or vss. 90 rst c reset input pin 86 hst c hardware standby input pin 95 to 102 p00 to p07 d in single chip mode, these are general purpose i/o pins. when set for input, they can be set by the pull-up resistance setting register (rdr0). when set for output, this setting will be invalid. ad00 to ad07 in external bus mode, these pins function as address low output/data low i/o pins. 103 to 110 p10 to p17 d in single chip mode, these are general purpose i/o pins. when set for input, they can be set by the pull-up resistance setting register (rdr1). when set for output, the setting will be invalid. ad08 to ad15 in external bus mode, these pins function as address middle output/data high i/o pins. 111 to 118 p20 to p27 e in single chip mode this is a general-purpose i/o port. a16 to a23 in external bus mode, these pins function as address high output pins. 120 p30 e in single chip mode this is a general-purpose i/o port. ale in external bus mode, this pin functions as the address latch enable signal output pin. 1p31 e in single chip mode this is a general-purpose i/o port. rd in external bus mode, this pin functions as the read strobe signal output pin. 2p32 e in single chip mode this is a general-purpose i/o port. wrl in external bus mode, this pin functions as the data bus lower 8-bit write strobe signal output pin. 3p33 e in single chip mode this is a general-purpose i/o port. wrh in external bus mode, this pin functions as the data bus upper 8-bit write strobe signal output pin. 4p34 e in single chip mode this is a general-purpose i/o port. hrq in external bus mode, this pin functions as the hold request signal input pin. 5p35 e in single chip mode this is a general-purpose i/o port. hak in external bus mode, this pin functions as the hold acknowledge signal output pin. 6p36 e in single chip mode this is a general-purpose i/o port. rdy in external bus mode, this pin functions as the ready signal input pin. *1: fpt-120p-m05 *2: fpt-120p-m13 , fpt-120p-m21 (continued)
9 mb90570 series pin no. pin name circuit type function lqfp-120 * 1 qfp-120 * 2 7p37 e in single chip mode this is a general-purpose i/o port. clk in external bus mode, this pin functions as the clock (clk) signal output pin. 9p40 f in single chip mode this is a general-purpose i/o port. it can be set to open drain by the odr4 register. sin0 this is also the uart ch.0 serial data input pin. while uart ch.0 is in input operation, this input signal is in continuous use, and therefore the output function should only be used when needed. if shared by output from other functions, this pin should be output disabled during sin operation. 10 p41 f in single chip mode this is a general-purpose i/o port. it can be set to open drain by the odr4 register. sot0 this is also the uart ch.0 serial data output pin. this function is valid when uart ch.0 is enabled for data output. 11 p42 f in single chip mode this is a general-purpose i/o port. it can be set to open drain by the odr4 register. sck0 this is also the uart ch.0 serial clock i/o pin. this function is valid when uart ch.0 is enabled for clock output. 12 p43 f in single chip mode this is a general-purpose i/o port. it can be set to open-drain by the odr4 register. sin1 this is also the uart ch.1 serial data input pin. while uart ch.1 is in input operation, this input signal is in continuous use, and therefore the output function should only be used when needed. if shared by output from other functions, this pin should be output disabled during sin operation. 13 p44 f in single chip mode this is a general-purpose i/o port. it can be set to opendrain by the odr4 register. sot1 this is also the uart ch.1 serial data output pin. this function is valid when uart ch.1 is enabled for data output. 14 p45 f in single chip mode this is a general-purpose i/o port. it can be set to open drain by the odr4 register. sck1 this is also the uart ch.1 serial clock i/o pin. this function is valid when uart ch.1 is enabled for clock output. 15,16 p46,p47 f in single chip mode this is a general-purpose i/o port. it can be set to open drain by the odr4 register. ppg0,ppg1 these are also the ppg0, 1 output pins. this function is valid when ppg0, 1 output is enabled. 17 p50 e in single chip mode this is a general-purpose i/o port. sin2 this is also the i/o serial ch.0 data input pin. during serial data input, this input signal is in continuous use, and therefore the output function should only be used when needed. *1: fpt-120p-m05 *2: fpt-120p-m13 , fpt-120p-m21 (continued)
10 mb90570 series pin no. pin name circuit type function lqfp-120 * 1 qfp-120 * 2 18 p51 e in single chip mode this is a general-purpose i/o port. sot2 this is also the i/o serial ch.0 data output pin. this function is valid when serial ch.0 is enabled for serial data output. 19 p52 e in single chip mode this is a general-purpose i/o port. sck2 this is also the i/o serial ch.0 clock i/o pin. this function is valid when serial ch.0 is enabled for serial data output. 20 p53 e in single chip mode this is a general-purpose i/o port. sin3 this is also the i/o serial ch.1 data input pin. during serial data input, this input signal is in continuous use, and therefore the output function should only be used when needed. 21 p54 e in single chip mode this is a general-purpose i/o port. sot3 this is also the i/o serial ch.1 data output pin. this function is valid when serial ch.1 is enabled for serial data output. 22 p55 e in single chip mode this is a general-purpose i/o port. sck3 this is also the i/o serial ch.1 clock i/o pin. this function is valid when serial ch.1 is enabled for serial data output. 23,24 p56,p57 e in single chip mode this is a general-purpose i/o port. in0,in1 these are also the input capture ch.0/1 trigger input pins. during input capture signal input on ch.0/1 this function is in continuous use, and therefore the output function should only be used when needed. 25 p60 f in single chip mode this is a general-purpose i/o port. when set for input it can be set by the pull-up resistance register (rdr6). when set for output this setting will be invalid. sin4 this is also the i/o serial ch.2 data input pin. during serial data input this function is in continuous use, and therefore the output function should only be used when needed. 26 p61 f in single chip mode this is a general-purpose i/o port. when set for input it can be set by the pull-up resistance register (rdr6). when set for output this setting will be invalid. sot4 this is also the i/o serial ch.2 data output pin. this function is valid when serial ch.2 is enabled for serial data output. 27 p62 f in single chip mode this is a general-purpose i/o port. when set for input it can be set by the pull-up resistance register (rdr6). when set for output this setting will be invalid. sck4 this is also the i/o serial ch.2 serial clock i/o pin. this function is valid when serial ch.2 is enabled for serial data output. 28 p63 f in single chip mode this is a general-purpose i/o port. when set for input it can be set by the pull-up resistance register (rdr6). when set for output this setting will be invalid. ckot this is also the clock monitor output pin. this function is valid when clock monitor output is enabled. *1: fpt-120p-m05 *2: fpt-120p-m13 , fpt-120p-m21 (continued)
11 mb90570 series pin no. pin name circuit type function lqfp-120 * 1 qfp-120 * 2 29 to 32 p64 to p67 f in single chip mode these are general-purpose i/o ports. when set for input they can be set by the pull-up resistance register (rdr6). when set for output this setting will be invalid. out0 to out3 these are also the output compare ch.0 to ch.3 event output pins. this function is valid when the respective channel(s) are enabled for output. 35 to 37 p70 to p72 e these are general purpose i/o ports. 40,41 p73,p74 i these are general purpose i/o ports. da0,da1 these are also the d/a converter ch.0,1 analog signal output pins. 46 to 53 p80 to p87 k these are general purpose i/o ports. an0 to an7 these are also a/d converter analog input pins. this function is valid when analog input is enabled. 55 to 62 p90 to p97 e these are general purpose i/o ports. cs0 to cs7 these are also chip select signal output pins. this function is valid when chip select signal output is enabled. 34 c g this is the power supply stabilization capacitor pin. it should be connected externally to an 0.1 f ceramic capacitor. note that this is not required on the flash model (mb90f574/a) and MB90574C. 64 pa0 e this is a general purpose i/o port. ain0 this pin is also used as count clock a input for 8/16-bit up-down counter ch.0. irq6 this pin can also be used as interrupt request input ch. 6. 65 pa1 e this is a general purpose i/o port. bin0 this pin is also used as count clock b input for 8/16-bit up-down counter ch.0. 66 pa2 e this is a general purpose i/o port. zin0 this pin is also used as count clock z input for 8/16-bit up-down counter ch.0. 67 pa3 e this is a general purpose i/o port. ain1 this pin is also used as count clock a input for 8/16-bit up-down counter ch.1. irq7 this pin can also be used as interrupt request input ch.7. 68 pa4 e this is a general purpose i/o port. bin1 this pin is also used as count clock b input for 8/16-bit up-down counter ch.1. 69 pa5 e this is a general purpose i/o port. zin1 this pin is also used as count clock z input for 8/16-bit up-down counter ch.1. *1: fpt-120p-m05 *2: fpt-120p-m13 , fpt-120p-m21 (continued)
12 mb90570 series (continued) pin no. pin name circuit type function lqfp-120 * 1 qfp-120 * 2 70 pa6 l this is a general purpose i/o port. sda this pin is also used as the data i/o pin for the i 2 c interface. this function is valid when the i 2 c interface is enabled for operation. while the i 2 c interface is operating, this port should be set to the input level (ddra: bit6 = 0). 71 pa7 l this is a general purpose i/o port. scl this pin is also used as the clock i/o pin for the i 2 c interface. this function is valid when the i 2 c interface is enabled for operation. while the i 2 c interface is operating, this port should be set to the input level (ddra: bit7 = 0). 72, 75 to 79 pb0, pb1 to pb5 e these are general-purpose i/o ports. irq0, irq1 to irq5 these pins are also the external interrupt input pins. irq0, 1 are enabled for both rising and falling edge detection, and therefore cannot be used for recovery from stop status for mb90v570, mb90f574, mb90573 and mb90574. however, irq0, 1 can be used for recovery from stop status for mb90v570a, mb90f574a and MB90574C. 80 pb6 e this is a general purpose i/o port. adtg this is also the a/d converter external trigger input pin. while the a/d converter is in input operation, this input signal is in continuous use, and therefore the output function should only be used when needed. 81 pb7 e this is a general purpose i/o port. 82 to 85 pc0 to pc3 e these are general purpose i/o ports. 8,54,94 v cc power supply these are power supply (5v) input pins. 33,63, 91,119 v ss power supply these are power supply (0v) input pins. 42 av cc h this is the analog macro (d/a, a/d etc.) vcc power supply input pin. 43 avrh j this is the a/d converter vref+ input pin. the input voltage should not exceed vcc. 44 avrl h this is the a/d converter vref-input pin. the input voltage should not less than vss. 45 av ss h this is the analog macro (d/a, a/d etc.) vss power supply input pin. 38 dv cc h this is the d/a converter vref input pin. the input voltage should not exceed vcc. 39 dv ss h this is the d/a converter gnd power supply pin. it should be set to vss equivalent potential. *1: fpt-120p-m05 *2: fpt-120p-m13 , fpt-120p-m21
13 mb90570 series n i/o circuit type (continued) type circuit remarks a ? oscillator circuit oscillator recovery resistance for high speed = approx. 1 m w b ? oscillator circuit oscillator recovery resistance for low speed = approx. 1 m w c ? hysteresis input pin resistance value = approx. 50 k w (typ.) d ? cmos hysteresis input pin with input pull- up control ? cmos level output. ? cmos hysteresis input (includes input shut down standby control function) ? pull-up resistance value = approx. 50 k w (typ.) i ol = 4ma x1 x0 standby control signal x1a x0a standby control signal hysteresis input r r hysteresis input selective signal either with a pull-up resistor or without it. i ol = 4 ma standby control for input interruption v cc v cc p-ch p-ch n-ch
14 mb90570 series (continued) type circuit remarks e ? cmos hysteresis input/output pin. ? cmos level output ? cmos hysteresis input (includes input shut down standby control function) i ol = 4 ma f ? cmos hysteresis input/output pin. ? cmos level output ? cmos hysteresis input (includes input shut down standby control function) i ol = 10 ma (large current port) g ? c pin output (capacitance connector pin). on the mb90f574 this pin is not connected (nc). h ? analog power supply protector circuit. i ? cmos hysteresis input/output ? analog output/cmos output dual-function pin (cmos output is not available during analog output.) (analog output priority: dae = 1) ? includes input shout down standby control function. i ol = 4ma v cc i ol = 4 ma r hysteresis input standby control for input interruption p-ch n-ch hysteresis input r i ol = 10 ma v cc standby control for input interruption p-ch n-ch v cc n-ch p-ch avp v cc p-ch n-ch r i ol = 4 ma hysteresis input dao standby control for input interruption v cc p-ch n-ch
15 mb90570 series type circuit remarks j ? a/d converter ref+ power supply input pin(avrh), with power supply protector circuit. k ? cmos hysteresis input /analog input dual-function pin. ? cmos output ? includes input shut down function at input shut down standby. l ? hysteresis input ? n-ch open-drain output ? includes input shut down standby control function. i ol = 4ma ane ane avr v cc p-ch n-ch n-ch p-ch hysteresis input r i ol = 4 ma analog input standby control for input interruption v cc n-ch p-ch hysteresis input r i ol = 4 ma standby control for input interruption v cc n-ch n-ch
16 mb90570 series n handling devices 1. preventing latchup cmos ics may cause latchup in the following situations: ? when a voltage higher than vcc or lower than vss is applied to input or output pins. ? when a voltage exceeding the rating is applied between vcc and vss. ? when avcc power is supplied prior to the vcc voltage. in turning on/turning off the analog power supply, make sure the analog power voltage (av cc , avrh, dv cc )and analog input voltages not exceed the digital voltage (v cc ). 2. treatment of unused pins leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device. therefor they must be tied to v cc or ground through resistors. in this case those resistors should be more than 2 kw. unused bidirectional pins should be set to the output state and can be left open, or the input state with the above described connection. 3. notes on using external clock in using the external clock, drive x0 pin only and leave x1 pin unconnected. 4. unused sub clock mode if sub clock modes are not used, the oscillator should be connected to the x01a pin and x1a pin 5. power supply pins (v cc /v ss ) in products with multiple v cc or v ss pins, the pins of a same potential are internally connected in the device to avoid abnormal operations including latch-up. however, connect the pins external power and ground lines to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating. make sure to connect v cc and v ss pins via lowest impedance to power lines. ? using external clock mb90570 series x0 x1 open
17 mb90570 series it is recommended to provide a bypass capacitor of around 0.1 m f between v cc and v ss pin near the device. 6. crystal oscillator circuit noises around x0 or x1 pins may be possible causes of abnormal operations. make sure to provide bypass capacitors via shortest distance from x0, x1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit do not cross the lines of other circuits. it is highly recommended to provide a printed circuit board art work surrounding x0 and x1 pins with an grand area for stabilizing the operation. 7. turning-on sequence of power supply to a/d converter and analog inputs make sure to turn on the a/d converter power supply, d/a converter power supply (av cc , avrh, avrl, dv cc ,dv ss ) and analog inputs (an0 to an7) after turning-on the digital power supply (v cc ). turn-off the digital power after turning off the a/d converter supply and analog inputs. in this case, make sure that the voltage does not exceed avrh or av cc (turning on/off the analog and digital power supplies simulta- neously is acceptable). 8. connection of unused pins of a/d converter connect unused pins of a/d converter to av cc = v cc , av ss = avrh = dv cc = v ss . 9. n.c. pins the n.c. (internally connected) pins must be opened for use. 10. notes on energization to prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 or more m s (0.2 v to 2.7 v). 11. indeterminate outputs from ports 0 and 1 the outputs from ports 0 and 1 become indeterminate during oscillation setting time of step-down circuit (during a power-on reset) after the power is turned on. (mb90573, mb90574, mb90v570, mb90v570a) v cc v cc v cc v cc v cc v ss v ss v ss v ss v ss ? using power supply pins mb90570 series
18 mb90570 series the series without built-in step-down circuit have no oscillation setting time of step-down circuit, so outputs should not become indeterminate. (mb90f574,mb90f574a,MB90574C) 12. initialization in the device, there are internal registers which are initialized only by a power-on reset. turn on the power again to initialize these registers. 13. return from standby state if the power-supply voltage goes below the standby ram holding voltage in the standby state, the device may fail to return from the standby state. in this case, reset the device via the external reset pin to return to the normal state. 14. precautions for use of div a, ri, and divw a, ri instructions the signed multiplication-division instructions div a, ri, and divw a, rwi should be used when the corre- sponding bank registers (dtb, adb, usb, ssb) are set to value 00h. if the corresponding bank registers (dtb, adb, usb, ssb) are set to a value other than 00h, then the remainder obtained after the execution of the instruction will not be placed in the instruction operand register. 15. precautions for use of realos extended intelligent i/o service (ei 2 os) cannot be used, when realos is used. oscillation setting time * 2 v cc (power-supply pin) ponr (power-on reset) signal rst (external asynchronous reset) signal rst (internal reset) signal oscillation clock signal ka (internal operating clock a) signal kb (internal operating clock b) signal port (port output) signal step-down circuit setting time * 1 period of indeterminate *1: step-down circuit setting time 2 17 /oscillation clock frequency (oscillation clock frequency of 16 mhz: 8.19 ms) *2: oscillation setting time 2 18 /oscillation clock frequency (oscillation clock frequency of 16 mhz: 16.38 ms) timing chart of indeterminate outputs from ports 0 and 1
19 mb90570 series n block diagram port 0, 1, 2 f 2 mcC16lx cpu clock control block (including timebase timer) external bus interface uart0 (sci), uart1 (sci) 16-bit free run timer interrupt controller 8-bit d/a converter 2 ch. internal data bus dtp/ external interrupt circuit 8 ch. input capture (icu) x0, x1 p00/ad00 to p07/ad07 dv ss port 3 port 4 8/16-bit ppg timer ch.0 port 5 sio 2 ch output compare (ocu) port 6 clock output x0a, x1a rst hst p10/ad08 to p17/ad15 p20/a16 to p27/a23 p30/ale p31/rd p32/wrl p33/wrh p36/rdy p35/hak p34/hrq p37/clk p40/sin0 p41/sot0 p42/sck0 p43/sin1 p44/sot1 p45/sck1 p46/ppg0 p47/ppg1 p50/sin2 p51/sot2 p52/sck2 p53/sin3 p54/sot3 p55/sck3 p56/in0 p57/in1 p64/out0 to p67/out3 p60/sin4 p61/sot4 p62/sck4 p63/ckot port 7 port 9 i 2 c bus port a chip select output port b port c ram p70 to p72 p73/da0 p74/da1 dv cc pa1/bin0 pa2/zin0 pa3/ain1/irq7 pa4/bin1 pa5/zin1 sio 1 ch. rom pa6/sda pa7/scl pb7 pb6/adtg pc0 to pc3 4 8 8 8 p00 to p07 (8 ports): provided with a register optional input pull-up resistor p10 to p17 (8 ports): provided with a register optional input pull-up resistor p40 to p47 (8 ports): heavy-current (i ol = 10 ma) port p60 to p67 (8 ports): provided with a register optional input pull-up resistor md0 to md2, c, v cc , v ss other pins main clock sub clock 8/16-bit up/down counter/timer 8 16 2 6 2 2 2 2 2 2 2 4 3 2 8 8 2 6 6 6 8 8/10-bit a/d converter 8 ch. port 8 p90/cs0 to p97/cs7 pa0/ain0/irq6 pb0/irq0 to pb5/irq5 avrl avrh av ss av cc p80/an0 to p87/an7 4 8
20 mb90570 series n memory map note: the rom data of bank ff is reflected in the upper address of bank 00, realizing effective use of the c compiler small model. the lower 16-bit of bank ff and the lower 16-bit of bank 00 is assigned to the same address, enabling reference of the table on the rom without stating far. for example, if an attempt has been made to access 00c000 h , the contents of the rom at ffc000 h are accessed actually. since the rom area of the ff bank exceeds 48 kbytes, the whole area cannot be reflected in the image for the 00 bank. the rom data at ff4000 h to ffffff h looks, therefore, as if it were the image for 00400 h to 00ffff h . thus, it is recommended that the rom data table be stored in the area of ff4000 h to ffffff h . part number address #1* address #2 * address #3 * mb90573 fe0000 h 004000 h 001800 h mb90574/c fc0000 h 004000 h 002900 h mb90f574/a fc0000 h 004000 h 002900 h ffffff h address #1 fc0000 h 010000 h address #2 address #3 000100 h 0000c0 h 000000 h rom area rom area rom area (image of bank ff) rom area (image of bank ff) ram ram ram register register register peripheral peripheral peripheral internal rom external bus mode a mirror function is supported. external rom external bus mode : internal access memory : external access memory *: addresses #1, #2 and #3 are unique to the product type. : inhibited area 004000 h single chip mode a mirror function is supported.
21 mb90570 series n f 2 mc-16lx cpu programming model ? dedicated registers : accumulator (a) dual 16-bit register used for storing results of calculation etc. the two 16-bit registers can be combined to be used as a 32-bit register. : additional data bank register (adb) the 8-bit register indicating the additional data space. : user stack pointer (usp) the 16-bit pointer indicating a user stack address. : user stack bank register (usb) the 8-bit register indicating the user stack space. : system stack pointer (ssp) the 16-bit pointer indicating the status of the system stack address. : processor status (ps) the 16-bit register indicating the system status. : program bank register (pcb) the 8-bit register indicating the program space. : data bank register (dtb) the 8-bit register indicating the data space. : program counter (pc) the 16-bit register indicating storing location of the current instruction code. : direct page register (dpr) the 8-bit register indicating bit 8 through 15 of the operand address in the short direct addressing mode. : system stack bank register (ssb) the 8-bit register indicating the system stack space. ah al usp ssp dpr pcb dtb usb ssb adb ps pc 8-bit 16-bit 32-bit
22 mb90570 series ? general-purpose registers ? processor status (ps) maximum of 32 banks 000180 h + (rp 10 h ) r7 r5 r3 r1 r6 r4 r2 r0 rw7 rw6 rw5 rw4 rl3 rl2 rl1 rl0 rw3 rw2 rw1 rw0 16-bit ilm rp ccr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ilm2 b4 ilm1 ilm0 b3 b2 b1 b0 i s t n z v c 00 000 0 00 1 0xxx x x ps initial value : reserved x : undefined
23 mb90570 series n i/o map (continued) address abbreviated register name register name read/ write resource name initial value 000000 h pdr0 port 0 data register r/w port 0 x x x x x x x x b 000001 h pdr1 port 1 data register r/w port 1 x x x x x x x x b 000002 h pdr2 port 2 data register r/w port 2 x x x x x x x x b 000003 h pdr3 port 3 data register r/w port 3 x x x x x x x x b 000004 h pdr4 port 4 data register r/w port 4 x x x x x x x x b 000005 h pdr5 port 5 data register r/w port 5 x x x x x x x x b 000006 h pdr6 port 6 data register r/w port 6 x x x x x x x x b 000007 h pdr7 port 7 data register r/w port 7 x x x x x x x x b 000008 h pdr8 port 8 data register r/w port 8 x x x x x x x x b 000009 h pdr9 port 9 data register r/w port 9 x x x x x x x x b 00000a h pdra port a data register r/w port a x x x x x x x x b 00000b h pdrb port b data register r/w port b x x x x x x x x b 00000c h pdrc port c data register r/w port c x x x x x x x x b 00000d h to 00000f h (disabled) 000010 h ddr0 port 0 direction register r/w port 0 0 0 0 0 0 0 0 0 b 000011 h ddr1 port 1 direction register r/w port 1 0 0 0 0 0 0 0 0 b 000012 h ddr2 port 2 direction register r/w port 2 0 0 0 0 0 0 0 0 b 000013 h ddr3 port 3 direction register r/w port 3 0 0 0 0 0 0 0 0 b 000014 h ddr4 port 4 direction register r/w port 4 0 0 0 0 0 0 0 0 b 000015 h ddr5 port 5 direction register r/w port 5 0 0 0 0 0 0 0 0 b 000016 h ddr6 port 6 direction register r/w port 6 0 0 0 0 0 0 0 0 b 000017 h ddr7 port 7 direction register r/w port 7 C C C 0 0 0 0 0 b 000018 h ddr8 port 8 direction register r/w port 8 0 0 0 0 0 0 0 0 b 000019 h ddr9 port 9 direction register r/w port 9 0 0 0 0 0 0 0 0 b 00001a h ddra port a direction register r/w port a 0 0 0 0 0 0 0 0 b 00001b h ddrb port b direction register r/w port b 0 0 0 0 0 0 0 0 b 00001c h ddrc port c direction register r/w port c 0 0 0 0 0 0 0 0 b 00001d h odr4 port 4 output pin register r/w port 4 0 0 0 0 0 0 0 0 b 00001e h ader analog input enable register r/w port 8, 8/10-bit a/d converter 11111111 b 00001f h (disabled) 000020 h smr0 serial mode register 0 r/w uart0 (sci) 00000000 b 000021 h scr0 serial control register 0 r/w 0 0 0 0 0 1 0 0 b
24 mb90570 series (continued) address abbreviated register name register name read/ write resource name initial value 000022 h sidr0/ sodr0 serial input data register 0/ serial output data register 0 r/w uart0 (sci) xxxxxxxx b 000023 h ssr0 serial status register 0 r/w 0 0 0 0 1 C 0 0 b 000024 h smr1 serial mode register 1 r/w uart1 (sci) 00000000 b 000025 h scr1 serial control register 1 r/w 0 0 0 0 0 1 0 0 b 000026 h sidr1/ sodr1 serial input data register 1/ serial output data register 1 r/w xxxxxxxx b 000027 h ssr1 serial status register 1 r/w 0 0 0 0 1 C 0 0 b 000028 h cdcr0 communications prescaler control register 0 r/w communica- tions prescaler register 0 0CCC1111 b 000029 h (disabled) 00002a h cdcr1 communications prescaler control register 1 r/w communica- tions prescaler register 0 0CCC1111 b 00002b h to 00002f h (disabled) 000030 h enir dtp/interrupt enable register r/w dtp/external interrupt cir- cuit 00000000 b 000031 h eirr dtp/interrupt factor register r/w x x x x x x x x b 000032 h elvr request level setting register r/w 00000000 b 000033 h 00000000 b 000034 h (disabled) 000035 h 000036 h adcs1 a/d control status register lower digits r/w 8/10-bit a/d converter 00000000 b 000037 h adcs2 a/d control status register upper digits r/w or w 00000000 b 000038 h adcr1 a/d data register lower digits r x x x x x x x x b 000039 h adcr2 a/d data register upper digits w 0 0 0 0 1 C x x b 00003a h dadr0 d/a converter data register ch.0 r/w 8-bit d/a converter xxxxxxxx b 00003b h dadr1 d/a converter data register ch.1 r/w x x x x x x x x b 00003c h dacr0 d/a control register 0 r/w CCCCCCC0 b 00003d h dacr1 d/a control register 1 r/w CCCCCCC0 b 00003e h clkr clock output enable register r/w clock monitor function CCCC0000 b 00003f h (disabled) 000040 h prll0 ppg0 reload register l ch.0 r/w 8/16-bit ppg timer 0 xxxxxxxx b 000041 h prlh0 ppg0 reload register h ch.0 r/w x x x x x x x x b
25 mb90570 series (continued) address abbreviated register name register name read/ write resource name initial value 000042 h prll1 ppg1 reload register l ch.1 r/w 8/16-bit ppg timer 1 xxxxxxxx b 000043 h prlh1 ppg1 reload register h ch.1 r/w x x x x x x x x b 000044 h ppgc0 ppg0 operating mode control register ch.0 r/w 8/16-bit ppg timer 0 0x000xx1 b 000045 h ppgc1 ppg1 operating mode control register ch.1 r/w 8/16-bit ppg timer 1 0x000001 b 000046 h ppgoe ppg0 and 1 output control registers ch.0 and ch.1 r/w 8/16-bit ppg timer 0, 1 000000xx b 000047 h (disabled) 000048 h smcsl0 serial mode control lower status register 0 r/w extended i/o serial interface 0 CCCC0000 b 000049 h smcsh0 serial mode control upper status register 0 r/w 00000010 b 00004a h sdr0 serial data register 0 r/w x x x x x x x x b 00004b h (disabled) 00004c h smcsl1 serial mode control lower status register 1 r/w extended i/o serial interface 1 CCCC0000 b 00004d h smcsh1 serial mode control upper status register 1 r/w 00000010 b 00004e h sdr1 serial data register 1 r/w x x x x x x x x b 00004f h (disabled) 000050 h ipcp0 icu data register ch.0 r 16-bit i/o timer (input capture (icu) section) xxxxxxxx b 000051 h xxxxxxxx b 000052 h ipcp1 icu data register ch.1 r xxxxxxxx b 000053 h xxxxxxxx b 000054 h ics01 icu control status register r/w 0 0 0 0 0 0 0 0 b 000055 h (disabled) 000056 h tcdt free run timer data register r/w 16-bit i/o timer (16-bit free run timer section) 00000000 b 000057 h 00000000 b 000058 h tccs free run timer control status register r/w 0 0 0 0 0 0 0 0 b 000059 h (disabled) 00005a h occp0 ocu compare register ch.0 r/w 16-bit i/o timer (output compare (ocu) section) xxxxxxxx b 00005b h xxxxxxxx b 00005c h occp1 ocu compare register ch.1 r/w xxxxxxxx b 00005d h xxxxxxxx b 00005e h occp2 ocu compare register ch.2 r/w xxxxxxxx b 00005f h xxxxxxxx b
26 mb90570 series (continued) address abbreviated register name register name read/ write resource name initial value 000060 h occp3 ocu compare register ch.3 r/w 16-bit i/o timer (output compare (ocu) section) xxxxxxxx b 000061 h xxxxxxxx b 000062 h ocs0 ocu control status register ch.0 r/w 0 0 0 0 C C 0 0 b 000063 h ocs1 ocu control status register ch.1 r/w C C C 0 0 0 0 0 b 000064 h ocs2 ocu control status register ch.2 r/w 0 0 0 0 C C 0 0 b 000065 h ocs3 ocu control status register ch.3 r/w C C C 0 0 0 0 0 b 000066 h (disabled) 000067 h 000068 h ibsr i 2 c bus status register r i 2 c interface 00000000 b 000069 h ibcr i 2 c bus control register r/w 00000000 b 00006a h iccr i 2 c bus clock control register r/w C C 0xxxxx b 00006b h iadr i 2 c bus address register r/w Cxxxxxxx b 00006c h idar i 2 c bus data register r/w xxxxxxxx b 00006d h (disabled) 00006e h 00006f h romm rom mirroring function selection register w rom mirroring function selection module CCCCCCC1 b 000070 h udcr0 up/down count register 0 r 8/16-bit up/down counter/timer 00000000 b 000071 h udcr1 up/down count register 1 r 0 0 0 0 0 0 0 0 b 000072 h rcr0 reload compare register 0 w 0 0 0 0 0 0 0 0 b 000073 h rcr1 reload compare register 1 w 0 0 0 0 0 0 0 0 b 000074 h csr0 counter status register 0 r/w 0 0 0 0 0 0 0 0 b 000075 h (reserved area)* 3 000076 h ccrl0 counter control register 0 r/w 8/16-bit up/down counter/timer C0000000 b 000077 h ccrh0 0 0 0 0 0 0 0 0 b 000078 h csr1 counter status register 1 r/w 0 0 0 0 0 0 0 0 b 000079 h (reserved area)* 3 00007a h ccrl1 counter control register 1 r/w 8/16-bit up/down counter/timer C0000000 b 00007b h ccrh1 C 0 0 0 0 0 0 0 b 00007c h smcsl2 serial mode control lower status register 2 r/w extended i/o serial interface 2 CCCC0000 b 00007d h smcsh2 serial mode control higher status register 2 r/w 00000010 b 00007e h sdr2 serial data register 2 r/w x x x x x x x x b 00007f h (disabled)
27 mb90570 series (continued) address abbreviated register name register name read/ write resource name initial value 000080 h cscr0 chip selection control register 0 r/w chip select output CCCC0000 b 000081 h cscr1 chip selection control register 1 r/w C C C C 0 0 0 0 b 000082 h cscr2 chip selection control register 2 r/w C C C C 0 0 0 0 b 000083 h cscr3 chip selection control register 3 r/w C C C C 0 0 0 0 b 000084 h cscr4 chip selection control register 4 r/w C C C C 0 0 0 0 b 000085 h cscr5 chip selection control register 5 r/w C C C C 0 0 0 0 b 000086 h cscr6 chip selection control register 6 r/w C C C C 0 0 0 0 b 000087 h to 00008b h (disabled) 00008c h rdr0 port 0 input pull-up resistor setup register r/w port 0 00000000 b 00008d h rdr1 port 1 input pull-up resistor setup register r/w port 1 00000000 b 00008e h rdr6 port 6 input pull-up resistor setup register r/w port 6 00000000 b 00008f h to 00009d h (disabled) 00009e h pacsr program address detection control status register r/w address match detection function 00000000 b 00009f h dirr delayed interrupt factor generation/ cancellation register r/w delayed interrupt generation module CCCCCCC0 b 0000a0 h lpmcr low-power consumption mode control register r/w low-power consumption (standby) mode 00011000 b 0000a1 h ckscr clock select register r/w 1 1 1 1 1 1 0 0 b 0000a2 h to 0000a4 h (disabled) 0000a5 h arsr automatic ready function select register w external bus pin 0011CC00 b 0000a6 h hacr upper address control register w 0 0 0 0 0 0 0 0 b 0000a7 h ecsr bus control signal select register w 0 0 0 0 0 0 0 0 b 0000a8 h wdtc watchdog timer control register r/w watchdog timer x x x x x x x x b 0000a9 h tbtc timebase timer control register r/w timebase timer 1 C C 0 0 1 0 0 b 0000aa h wtc clock timer control register r/w clock timer 1 x 0 0 0 0 0 0 b
28 mb90570 series (continued) address abbreviated register name register name read/ write resource name initial value 0000ab h to 0000ad h (disabled) 0000ae h fmcs flash control register r/w flash interface 0 0 0 x 0 x x 0 b 0000af h (disabled) 0000b0 h icr00 interrupt control register 00 r/w interrupt controller 00000111 b 0000b1 h icr01 interrupt control register 01 r/w 0 0 0 0 0 1 1 1 b 0000b2 h icr02 interrupt control register 02 r/w 0 0 0 0 0 1 1 1 b 0000b3 h icr03 interrupt control register 03 r/w 0 0 0 0 0 1 1 1 b 0000b4 h icr04 interrupt control register 04 r/w 0 0 0 0 0 1 1 1 b 0000b5 h icr05 interrupt control register 05 r/w 0 0 0 0 0 1 1 1 b 0000b6 h icr06 interrupt control register 06 r/w 0 0 0 0 0 1 1 1 b 0000b7 h icr07 interrupt control register 07 r/w 0 0 0 0 0 1 1 1 b 0000b8 h icr08 interrupt control register 08 r/w 0 0 0 0 0 1 1 1 b 0000b9 h icr09 interrupt control register 09 r/w 0 0 0 0 0 1 1 1 b 0000ba h icr10 interrupt control register 10 r/w 0 0 0 0 0 1 1 1 b 0000bb h icr11 interrupt control register 11 r/w 0 0 0 0 0 1 1 1 b 0000bc h icr12 interrupt control register 12 r/w 0 0 0 0 0 1 1 1 b 0000bd h icr13 interrupt control register 13 r/w 0 0 0 0 0 1 1 1 b 0000be h icr14 interrupt control register 14 r/w 0 0 0 0 0 1 1 1 b 0000bf h icr15 interrupt control register 15 r/w 0 0 0 0 0 1 1 1 b 0000c0 h to 0000ff h (external area)* 1 000100 h to 000### h (ram area)* 2 000### h to 001fef h (reserved area)* 3 001ff0 h padr0 program address detection register 0 r/w address match detection function xxxxxxxx b 001ff1 h program address detection register 1 r/w x x x x x x x x b 001ff2 h program address detection register 2 r/w x x x x x x x x b 001ff3 h padr1 program address detection register 3 r/w x x x x x x x x b 001ff4 h program address detection register 4 r/w x x x x x x x x b 001ff5 h program address detection register 5 r/w x x x x x x x x b 001ff6 h to 001fff h (reserved area)
29 mb90570 series descriptions for read/write r/w: readable and writable r: read only w: write only descriptions for initial value 0 : the initial value of this bit is 0. 1 : the initial value of this bit is 1. x : the initial value of this bit is undefined. C : this bit is unused. the initial value is undefined. *1: this area is the only external access area having an address of 0000ff h or lower. an access operation to this area is handled as that to external i/o area. *2: for details of the ram area, see n memory map. *3: the reserved area is disabled because it is used in the system. notes: ? for bits that is initialized by an reset operation, the initial value set by the reset operation is listed as an initial value. note that the values are different from reading results. for lpmcr/ckscr/wdtc, there are cases where initialization is performed or not performed, depending on the types of the reset. however initial value for resets that initializes the value are listed. ? the addresses following 0000ff h are reserved. no external bus access signal is generated. ? boundary #### h between the ram area and the reserved area varies with the product model.
30 mb90570 series n interrupt factors, interrupt vectors, interrupt control register (continued) interrupt source ei 2 os support interrupt vector interrupt control register priority number address icr address reset # 08 ffffdc h high int9 instruction # 09 ffffd8 h exception # 10 ffffd4 h 8/10-bit a/d converter # 11 ffffd0 h icr00 0000b0 h input capture 0 (icu) include # 12 ffffcc h dtp0 (external interrupt 0) # 13 ffffc8 h icr01 0000b1 h input capture 1 (icu) include # 14 ffffc4 h output compare 0 (ocu) match # 15 ffffc0 h icr02 0000b2 h output compare 1 (ocu) match # 16 ffffbc h output compare 2 (ocu) match # 17 ffffb8 h icr03 0000b3 h output compare 3 (ocu) match # 18 ffffb4 h extended i/o serial interface 0 # 19 ffffb0 h icr04 0000b4 h 16-bit free run timer # 20 ffffac h extended i/o serial interface 1 # 21 ffffa8 h icr05 0000b5 h clock timer # 22 ffffa4 h extended i/o serial interface 2 # 23 ffffa0 h icr06 0000b6 h dtp1 (external interrupt 1) # 24 ffff9c h dtp2/dtp3 (external interrupt 2/ external interrupt 3) # 25 ffff98 h icr07 0000b7 h 8/16-bit ppg timer 0 counter borrow # 26 ffff94 h dtp4/dtp5 (external interrupt 4/ external interrupt 5) # 27 ffff90 h icr08 0000b8 h 8/16-bit ppg timer 1 counter borrow # 28 ffff8c h 8/16-bit up/down counter/timer 0 borrow/overflow/inversion # 29 ffff88 h icr09 0000b9 h 8/16-bit up/down counter/timer 0 compare match # 30 ffff84 h 8/16-bit up/down counter/timer 1 borrow/overflow/inversion # 31 ffff80 h icr10 0000ba h 8/16-bit up/down counter/timer 1 compare match # 32 ffff7c h 0000ba h dtp6 (external interrupt 6) # 33 ffff78 h icr11 0000bb h timebase timer # 34 ffff74 h low
31 mb90570 series (continued) : can be used : can not be used : can be used. with ei 2 os stop function. interrupt source ei 2 os support interrupt vector interrupt control register priority number address icr address dtp7 (external interrupt 7) # 35 ffff70 h icr12 0000bc h high low i 2 c interface # 36 ffff6c h uart1 (sci) reception complete # 37 ffff68 h icr13 0000bd h uart1 (sci) transmission complete # 38 ffff64 h uart0 (sci) reception complete # 39 ffff60 h icr14 0000be h uart0 (sci) transmission complete # 40 ffff5c h flash memory # 41 ffff58 h icr15 0000bf h delayed interrupt generation module # 42 ffff54 h
32 mb90570 series n peripherals 1. i/o port (1) input/output port port 0 through 4, 6, 8, a and b are general-purpose i/o ports having a combined function as an external bus pin and a resource input. port 0 to port 3 have a general-purpose i/o ports function only in the single-chip mode. ? operation as output port the pin is configured as an output port by setting the corresponding bit of the ddr register to 1. writing data to pdr register when the port is configured as output, the data is retained in the output latch in the pdr and directly output to the pin. the value of the pin (the same value retained in the output latch of pdr) can be read out by reading the pdr register. note: when a read-modify-write instruction (e.g. bit set instruction) is performed to the port data register, the destination bit of the operation is set to the specified value, not affecting the bits configured by the ddr register for output, however, values of bits configured by the ddr register as inputs are changed because input values to the pins are written into the output latch. to avoid this situation, configure the pins by the ddr register as output after writing output data to the pdr register when configuring the bit used as input as outputs. ? operation as input port the pin is configured as an input by setting the corresponding bit of the ddr register to 0. when the pin is configured as an input, the output buffer is turned-off and the pin is put into a high-impedance status. when a data is written into the pdr register, the data is retained in the output latch of the pdr, but pin outputs are unaffected. reading the pdr register reads out the pin level (0 or 1).
33 mb90570 series (2) register configuration (continued) ? port 0 data register (pdr0) ? port 1 data register (pdr1) address 000000 h bit 15 bit 8 p07 p06 p05 p04 p03 p02 p01 p00 (pdr1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w ............ xxxxxxxx b bit 7 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............ r/w r/w r/w r/w r/w r/w r/w r/w (pdr0) address 000001 h initial value xxxxxxxx b initial value p17 p16 p15 p14 p13 p12 p11 p10 ? port 2 data register (pdr2) ? port 3 data register (pdr3) address 000002 h bit 15 bit 8 p27 p26 p25 p24 p23 p22 p21 p20 (pdr3) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w ............ xxxxxxxx b bit 7 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............ r/w r/w r/w r/w r/w r/w r/w r/w (pdr2) address 000003 h initial value xxxxxxxx b initial value p37 p36 p35 p34 p33 p32 p31 p30 ? port 4 data register (pdr4) ? port 5 data register (pdr5) address 000004 h bit 15 bit 8 p47 p46 p45 p44 p43 p42 p41 p40 (pdr5) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w ............ xxxxxxxx b bit 7 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............ r/w r/w r/w r/w r/w r/w r/w r/w (pdr4) address 000005 h initial value xxxxxxxx b initial value p57 p56 p55 p54 p53 p52 p51 p50 ? port 6 data register (pdr6) ? port 7 data register (pdr7) address 000006 h bit 15 bit 8 p67 p66 p65 p64 p63 p62 p61 p60 (pdr7) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w ............ xxxxxxxx b bit 7 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............ r/w r/w r/w r/w r/w (pdr6) address 000007 h initial value - - - xxxxx b initial value p74 p73 p72 p71 p70 ? port 8 data register (pdr8) address 000008 h bit 15 bit 8 p87 p86 p85 p84 p83 p82 p81 p80 (pdr9) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w ............ xxxxxxxx b initial value
34 mb90570 series (continued) ? port a data register (pdra) ? port 9 data register (pdr9) address 00000a h bit 15 bit 8 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 (pdrb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w ............ xxxxxxxx b bit 7 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............ r/w r/w r/w r/w r/w r/w r/w r/w (pdr8) initial value xxxxxxxx b initial value p97 p96 p95 p94 p93 p92 p91 p90 address 000009 h ? port b data register (pdrb) address 00000b h bit 15 bit 8 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 (pdra) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w ............ xxxxxxxx b initial value ? port c data register (pdrc) address 00000c h bit 15 bit 8 pc3 pc2 pc1 pc0 (disabled) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/wr/wr/wr/w ............ xxxxxxxx b initial value ? port 0 direction register (ddr0) address 000010 h bit 15 bit 8 d07 d06 d05 d04 d03 d02 d01 d00 (ddr1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w ............ 00000000 b initial value ? port 2 direction register (ddr2) address 000012 h bit 15 bit 8 d27 d26 d25 d24 d23 d22 d21 d20 (ddr3) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w ............ 00000000 b initial value ? port 4 direction register (ddr4) address 000014 h bit 15 bit 8 d47 d46 d45 d44 d43 d42 d41 d40 (ddr5) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w ............ 00000000 b initial value ? port 1 direction register (ddr1) bit 7 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............ r/w r/w r/w r/w r/w r/w r/w r/w (ddr0) 00000000 b initial value d17 d16 d15 d14 d13 d12 d11 d10 ? port 3 direction register (ddr3) bit 7 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............ r/w r/w r/w r/w r/w r/w r/w r/w (ddr2) 00000000 b initial value d37 d36 d35 d34 d33 d32 d31 d30 address 000011 h address 000013 h
35 mb90570 series (continued) ? port 6 direction register (ddr6) ? port 5 direction register (ddr5) address 000016 h bit 15 bit 8 d67 d66 d65 d64 d63 d62 d61 d60 (ddr7) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w ............ 00000000 b bit 7 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............ r/w r/w r/w r/w r/w r/w r/w r/w (ddr4) initial value 00000000 b initial value d57 d56 d55 d54 d53 d52 d51 d50 address 000015 h ? port 8 direction register (ddr8) address 000018 h bit 15 bit 8 d87 d86 d85 d84 d83 d82 d81 d80 (ddr9) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w ............ 00000000 b initial value ? port c direction register (ddrc) address 00001c h bit 15 bit 8 dc3 dc2 dc1 dc0 (odr4) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/wr/wr/wr/w ............ 00000000 b initial value ? port 0 input pull-up resistor setup register (rdr0) address 00008c h bit 15 bit 8 rd07 rd06 rd05 rd04 rd03 rd02 rd01 rd00 (rdr1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w ............ 00000000 b initial value ? port 9 direction register (ddr9) bit 7 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............ r/w r/w r/w r/w r/w r/w r/w r/w (ddr8) 00000000 b initial value d97 d96 d95 d94 d93 d92 d91 d90 address 000019 h ? port 7 direction register (ddr7) bit 7 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............ r/w r/w r/w r/w r/w (ddr6) - - - 00000 b initial value d74 d73 d72 d71 d70 address 000017 h ? port 4 output pin register (odr4) address 00001d h bit 15 bit 8 od47 od46 od45 od44 od43 od42 od41 od40 (ddrc) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w ............ 00000000 b initial value ? port a direction register (ddra) address 00001a h bit 15 bit 8 da7 da6 da5 da4 da3 da2 da1 da0 (ddrb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w ............ 00000000 b initial value ? port b direction register (ddrb) address 00001b h bit 15 bit 8 db7 db6 db5 db4 db3 db2 db1 db0 (ddra) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w ............ 00000000 b initial value
36 mb90570 series (continued) ? port 6 input pull-up resistor setup register (rdr6) ? port 1 input pull-up resistor setup register (rdr1) address 00008e h bit 15 bit 8 rd67 rd66 rd65 rd64 rd63 rd62 rd61 rd60 (disabled) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w ............ 00000000 b bit 7 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............ r/w r/w r/w r/w r/w r/w r/w r/w (rdr0) initial value 00000000 b initial value rd17 rd16 rd15 rd14 rd13 rd12 rd11 rd10 address 00008d h ? analog input enable register (ader) 11111111 b initial value (disabled) ade7 ade6 ade5 ade4 ade3 address 00001e h r/w : readable and writable :reserved x : undefined bit 15 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ............ ade2 ade1 ade0 r/w r/w r/w r/w r/w r/w r/w r/w
37 mb90570 series (3) block diagram ? input/output port pdr (port data register) ddr (port direction register) pdr read pdr write ddr write ddr read direction latch output latch internal data bus standby control: stop, timebase timer mode and spl=1, or hardware standby mode standby control (spl=1) p-ch n-ch pin ? output pin register (odr) to resource input ddr (port direction register) pdr read pdr write ddr write ddr read direction latch output latch internal data bus standby control: stop, timebase timer mode and spl=1, or hardware standby mode standby control (spl=1) p-ch n-ch pin odr (output pin register) odr write odr read odr latch pdr (port data register) from resource output resource output enable
38 mb90570 series ? input pull-up resistor setup register (rdr) to resource input ddr (port direction register) pdr read pdr write ddr write ddr read direction latch output latch internal data bus standby control: stop, timebase timer mode and spl=1 standby control (spl=1) p-ch n-ch pin rdr (input pull-up resistor setup register) rdr write rdr read rdr latch pdr (port data register) pull-up resistor about 5.0 k w (5.0 v) p-ch ? analog input enable register (ader) pdr (port data register) ader read ader write pdr write pdr read ader latch internal data bus standby control (spl=1) p-ch n-ch pin ddr write ddr read direction latch ader (analog input enable register) to analog input output latch rmw (read-modify-write type instruction) standby control: stop, timebase timer mode and spl=1 ddr (port direction register)
39 mb90570 series 2. timebase timer the timebase timer is a 18-bit free run counter (timebase counter) for counting up in synchronization to the internal count clock (divided-by-2 of oscillation) with an interval timer function for selecting an interval time from four types of 2 12 /hclk, 2 14 /hclk, 2 16 /hclk, and 2 19 /hclk. the timebase timer also has a function for supplying operating clocks for the timer output for the oscillation stabilization time or the watchdog timer etc. (1) register configuration (2) block diagram . . . . . . . . . . . . ? timebase timer control register (tbtc) resv bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 0 r/w r/w w r/w r/w (wdtc) initial value 1--00100 b address 0000a9 h tbie tbof tbr tbc1 tbc0 r/w : readable and writable w : write only : unused resv: reserved bit . . . . . . to 8/16-bit ppg timer timebase timer counter divided-by-2 of hclk power-on reset start stop mode ckscr: mcs = 1 ? 0* 1 counter clear circuit interval timer selector clear tbof set tbof timebase timer control register (tbtc) timebase timer interrupt signal #34* 2 of: overflow hclk: oscillation clock *1: switch machine clock from oscillation clock to pll clock *2: interrupt signal resv tbie tbr tbof tbc1 tbc0 to oscillation stabilization time selector of clock control block to watchdog timer of of of of 2 1 2 2 2 3 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18
40 mb90570 series 3. watchdog timer the watchdog timer is a 2-bit counter operating with an output of the timebase timer and resets the cpu when the counter is not cleared for a preset period of time. (1) register configuration (2) block diagram ? watchdog timer control register (wdtc) address 0000a8 h bit 15 bit 8 ponr stbr wrst erst srst wte wt1 wt0 (tbtc) r : read only w: write only x : indeterminate bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rrrr rwww ............ initial value xxxxxxxx b hclk: oscillation clock ponr stbr wrst erst srst wte wt1 wt0 watchdog timer control register (wdtc) start sleep mode start hold status start stop mode clr and start watchdog timer overflow to internal reset generation circuit counter clear control circuit count clock selector 2-bit counter watchdog timer reset generation circuit clear divided-by-2 of hclk (timebase timer counter) 2 1 2 2 ... 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 clr 2 4 clr
41 mb90570 series 4. 8/16-bit ppg timer the 8/16-bit ppg timer is a 2-ch reload timer module for outputting pulse having given frequencies/duty ratios. the two modules performs the following operation by combining functions. ? 8-bit ppg output 2-ch independent operation mode this is a mode for operating independent 2-ch 8-bit ppg timer, in which ppg0 and ppg1 pins correspond to outputs from ppg0 and ppg1 respectively. ? 16-bit ppg timer output operation mode in this mode, ppg0 and ppg1 are combined to be operated as a 1-ch 8/16-bit ppg timer operating as a 16- bit timer. because ppg0 and ppg1 outputs are reversed by an underflow from ppg1 outputting the same output pulses from ppg0 and ppg1 pins. ? 8 + 8-bit ppg timer output operation mode in this mode, ppg0 is operated as an 8-bit communications prescaler, in which an underflow output of ppg0 is used as a clock source for ppg1. a toggle output of ppg0 and ppg output of ppg1 are output from ppg0 and ppg1 respectively. ? ppg output operation a pulse wave with any period/duty ratio is output. the module can also be used as a d/a converter with an external add-on circuit.
42 mb90570 series (1) register configuration ? ppg0, 1 output control register ch.0, ch.1(ppgoe) ? ppg0 reload register h ch.0 (prlh0) address 000046 h bit 15 bit 8 pcs2 pcs1 pcs0 pcm2 pcm1 pcm0 (disabled) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w ............ bit 7 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............ (prlh0) r/w r/w r/w r/w r/w r/w r/w r/w 000000xx b bit 7 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............ r/w r/w r/w r/w r/w r/w r/w r/w (prll1) address 000041 h ? ppg1 reload register h ch.1 (prlh1) address 000043 h ? ppg0 reload register l ch.0 (prll0) ? ppg1 reload register l ch.1 (prll1) address 000040 h bit 15 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ............ (prlh1) r/w r/w r/w r/w r/w r/w r/w r/w address 000042 h bit 15 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ............ r/w r/w r/w r/w r/w r/w r/w r/w initial value xxxxxxxx b initial value xxxxxxxx b initial value ? ppg0 operating mode control register ch.0 (ppgc0) address 000044 h pen0 pe00 pie0 puf0 resv (ppgc1) 0x000xx1 b initial value bit 15 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ............ r/w r/w r/w r/w bit 7 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............ r/w r/w r/w r/w r/w r/w r/w r/w (ppgc0) address 000045 h 0x000001 b initial value pen1 pei0 pie1 puf1 md1 md0 resv ? ppg1 operating mode control register ch.1 (ppgc1) r/w : readable and writable :reserved x : undefined resv: reserved bit (prll0) xxxxxxxx b initial value xxxxxxxx b initial value
43 mb90570 series (2) block diagram ? block diagram of 8/16-bit ppg timer (ch.0) prlh0 timebase timer output (512/hclk) pen0 data bus for h digits pe00 pie0 puf0 resv data bus for l digits ppg0 operating mode control register ch.0 (ppgc0) ppg0 reload register prll0 temporary buffer (prlbh0) reload register (l/h selector) down counter (pcnt0) count value clear clk 2 select signal re-load underflow pulse selector ppg0 output latch reverse ppg output control circuit mode control signal pin p46/ppg0 count clock selector ppg1 underflow ppg0 underflow (to ppg1) select signal * : interrupt number hclk : oscillation clock f : machine clock frequency 3 r sq interrupt request #26* pcm2 pcm1 pcm0 peripheral clock (16/ f ) peripheral clock (8/ f ) peripheral clock (4/ f ) peripheral clock (2/ f ) peripheral clock (1/ f ) ppg0 output control register ch.0 (ppgoe0)
44 mb90570 series ? block diagram of 8/16-bit ppg timer (ch.1) * : interrupt number hclk : oscillation clock f : machine clock frequency pen1 data bus for h digits data bus for l digits ppg1 operating mode control register ch.1 (ppgc1) ppg1 output latch 2 reverse count clock selector select signal ppg0 underflow interrupt request #28* timebase timer output (512/hclk) peripheral clock (16/ f ) peripheral clock (8/ f ) peripheral clock (4/ f ) peripheral clock (2/ f ) peripheral clock (1/ f ) pei0 pie1 puf1 md1 md0 resv pcs2 pcs1 pcs0 ppg1 output control register ch.1 (ppgoe1) ppg1 underflow (to ppg0) prlh1 prll1 temporary buffer (prlbh1) reload selector (l/h selector) down counter (pcnt1) pin count value clear select signal re-load underflow ppg output control circuit p47/ppg1 ppg1 reload register operating mode control signal clk md0 r s q
45 mb90570 series 5. 16-bit i/o timer the 16-bit i/o timer module consists of one 16-bit free run timer, two input capture circuits, and four output comparators. this module allows two independent waveforms to be output on the basis of the 16-bit free run timer. input pulse width and external clock periods can, therefore, be measured. ?block diagram internal data bus input capture 16-bit free run timer output compare dedicated bus dedicated bus
46 mb90570 series (1) 16-bit free run timer the 16-bit free run timer consists of a 16-bit up counter, a control register, and a communications prescaler register. the value output from the timer counter is used as basic timer (base timer) for input capture (icu) and output compare (ocu). ? a counter operation clock can be selected from four internal clocks ( f /4, f /16, f /32 and f /64). ? an interrupt can be generated by overflow of counter value or compare match with ocu compare register 0. (compare match requires mode setup.) ? the counter value can be initialized to 0000 h by a reset, software clear or compare match with ocu compare register 0. ? register configuration ?block diagram ? free run timer data register (tcdt) bit 15 bit 8 ? free run timer control status register (tccs) ivf resv (disabled) r/w r/w r/w r/w r/w r/w r/w r/w bit 7 bit 6 bit 5 bit 4 initial value 00000000 b stop ivfe clr mode clk0 clk1 ............. bit 3 bit 2 bit 1 bit 0 r/w : readable and writable resv: reserved bit address 000058 h address 000056 h 000057 h bit 15 initial value 00000000 b bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t15 t14 t13 t12 t11 t10 t9 t8 t7 t6 t5 t4 t3 t2 t1 t0 free run timer data register (tcdt) 16-bit free run timer interrupt request #20* * : interrupt number f: machine clock frequency of : overflow 2 of free run timer control status register (tccs) f 16-bit counter stop clk clr communications prescaler register resv ivf ivfe stop mode clr clk1 clk0 ocu compare register ch.0 match signal internal data bus count value output to ico and ocu
47 mb90570 series (2) input capture (icu) the input capture (icu) generates an interrupt request to the cpu simultaneously with a storing operation of current counter value of the 16-bit free run timer to the icu data register (ipcp) upon an input of a trigger edge to the external pin. there are four sets (four channels) of the input capture external pins and icu data registers, enabling measurements of maximum of four events. ? the input capture has two sets of external input pins (in0, in1) and icu registers (ipcp), enabling measurements of maximum of four events. ? a trigger edge direction can be selected from rising/falling/both edges. ? the input capture can be set to generate an interrupt request at the storage timing of the counter value of the 16-bit free run timer to the icu data register (ipcp). ? the input compare conforms to the extended intelligent i/o service (ei 2 os). ? the input capture (icu) function is suited for measurements of intervals (frequencies) and pulse widths. ? register configuration ? icu data register ch.0, ch.1 (ipcp0, ipcp1) address initial value xxxxxxxx b cp15 cp14 cp13 cp12 cp11 cp10 cp09 cp08 (ipcp0 low, ipcp1 low) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 0 ............. rr rrrr rr address cp07 cp06 cp05 cp04 cp03 cp02 cp01 cp00 (ipcp0 high, ipcp1 high) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 8 ............ rr rrrr rr ? icu control status register (ics01) r/w : readable and writable r : read only x:undefined 000051 h 000053 h address 000054 h initial value 00000000 b icp1 icp0 ice1 ice0 eg11 eg10 eg01 eg00 (disabled) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 8 ............ r/w r/w r/w r/w r/w r/w r/w r/w 000050 h 000052 h note: this register holds a 16-bit free run timer value when the valid edge of the corresponding external pin input waveform is detected. (you can word-access this register, but you cannot program it.) initial value xxxxxxxx b ipcp0(low): ipcp1(low): ipcp0(high): ipcp1(high):
48 mb90570 series ?block diagram internal data bus edge detection circuit data latch signal latch signal output latch icu data register (ipcp) ipcp0h ipcp0l 16 16 16-bit free run timer 2 2 p56/in0 pin pin interrupt request #12* icp1 p57/in1 ipcp1h ipcp1l icp0 ice1 ice0 eg11 eg10 eg01 eg00 interrupt request #14* * : interrupt number icu control status register (ics01)
49 mb90570 series (3) output compare (ocu) the output compare (ocu) is two sets of compare units consisting of four-channel ocu compare registers, a comparator and a control register. an interrupt request can be generated for each channel upon a match detection by performing time-division comparison between the ocu compare data register setting value and the counter value of the 16-bit free run timer. the out pin can be used as a waveform output pin for reversing output upon a match detection or a general- purpose output port for directly outputting the setting value of the cmod bit. ? register configuration cmod ote1 ote0 otd1 otd0 (ocs0, ocs2) ? ocu control status register ch.1, ch.3 (ocs1, ocs3) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 0 r/w r/w r/w r/w r/w address initial value - - - 00000 b ............. icp1 icp0 ice1 ice0 cst1 cst0 (ocs1, ocs3) ? ocu control status register ch.0, ch.2 (ocs0, ocs2) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 8 r/w r/w r/w r/w r/w r/w ............ c15 c14 c13 c12 c11 c10 c09 c08 ? ocu compare register ch.0 to ch.3 (occp0 to occp3) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w r/w r/w r/w r/w r/w r/w r/w initial value xxxxxxxx b c07 c06 c05 c04 c03 c02 c01 c00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w : readable and writable :reserved x : undefined 000063 h 000065 h initial value 0000 - - 00 b address 000062 h 000064 h initial value xxxxxxxx b address occp0 (high order address): 00005b h occp1 (high order address): 00005d h occp2 (high order address): 00005f h occp3 (high order address): 000061 h address occp0 (low order address): 00005a h occp1 (low order address): 00005c h occp2 (low order address): 00005e h occp3 (low order address): 000060 h
50 mb90570 series ?block diagram ocu control status register ch.0 , ch.1 (ocs0, ocs1) 16-bit free run timer compare control circuit 3 occp3 #18* #17* output compare interrupt request output control circuit 3 pin p67/out3 * : interrupt number 2 2 cmod ote1 ote0 otd1 otd0 icp1 icp0 ice1 ice0 cst1 cst0 ocu compare register ch.3 compare control circuit 2 occp2 ocu compare register ch.2 compare control circuit 1 ocu compare register ch.1 compare control circuit 0 ocu compare register ch.0 occp1 occp0 internal data bus ocu control status register ch.2 , ch.3 (ocs2, ocs3) cmod ote1 ote0 otd1 otd0 icp1 icp0 ice1 ice0 cst1 cst0 #16* #15* output compare interrupt request output control circuit 2 output control circuit 1 output control circuit 0 pin p65/out1 pin p66/out2 pin p64/out0 2 2
51 mb90570 series 6. 8/16-bit up/down counter/timer the 8/16-bit up/down counter/timer consists of six event input pins, two 8-bit up/down counters, two 8-bit reload compare registers, and their controllers. (1) register configuration 000076 h 00007a h ? up/down count register 1 (udcr1) bit 7 bit 0 address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............. initial value 00000000 b d17 d16 d15 d14 d13 d12 d11 d10 (udcr0) rrrrrrrr ? up/down count register 0 (udcr0) bit 15 bit 8 address d06 d07 (udcr1) rrrrrrrr bit 7 bit 6 bit 5 bit 4 d04 d05 d02 d03 d00 d01 ............ bit 3 bit 2 bit 1 bit 0 000070 h initial value 00000000 b 000071 h ? reload compare register 1 (rcr1) bit 7 bit 0 address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............. initial value 00000000 b d17 d16 d15 d14 d13 d12 d11 d10 (rcr0) wwwwwwww ? reload compare register 0 (rcr0) bit 15 bit 8 address d06 d07 (rcr1) wwwwwwww bit 7 bit 6 bit 5 bit 4 d04 d05 d02 d03 d00 d01 ............ bit 3 bit 2 bit 1 bit 0 000072 h initial value 00000000 b 000073 h ? counter status register 0, 1 (csr0, csr1) bit 15 bit 8 address cite cstr (reserved area) r/w r/w r/w r/w r/w r/w r r bit 7 bit 6 bit 5 bit 4 cmpf udie udff ovff udf0 udf1 ............ bit 3 bit 2 bit 1 bit 0 000074 h 000078 h initial value 00000000 b ? counter control register 0, 1 (ccrl0, ccrl1) bit 15 bit 8 address ctut (ccrh0, ccrh1) r/w r/w r/w r/w r/w r/w r/w bit 7 bit 6 bit 5 bit 4 rlde ucre cgsc udcc cge0 cge1 ............ bit 3 bit 2 bit 1 bit 0 initial value - 0000000 b ? counter control register 0 (ccrh0) bit 7 bit 0 address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............. initial value 00000000 b m16e cdcf cfie clks cms1 cms0 ces1 ces0 (ccrl0) r/w r/w r/w r/w r/w r/w r/w r/w 000077 h ? counter control register 1 (ccrh1) bit 7 bit 0 address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............. initial value - 0000000 b cdcf cfie clks cms1 cms0 ces1 ces0 (ccrl1) r/w r/w r/w r/w r/w r/w r/w 00007b h r/w : readable and writable r : read only w : write only : undefined
52 mb90570 series (2) block diagram ? block diagram of 8/16-bit up/down counter/timer 0 internal data bus rcr0 reload compare register 0 re-load control circuit up/down count register 0 udcr0 carry/ borrw counter control register 0 (ccrl0) ctut cge1 cge0 ucre udcc rlde cgsc pa2/zin0 pin edge/level detection circuit counter clear circuit overflow underflow compare control circuit prescaler pa0/ain0/irq6 pin pin pa1/bin0 up/down count clock selector counter status register 0 (csr0) count clock cstr cite udie cmpf ovff udff udf1 udf0 m16e cdcf ces1 ces0 cfie cms1 clks cms0 interrupt request #29* interrupt request #30* counter control register 0 (ccrh0) m16e (to channel 1) (to channel 1) * : interrupt number f : machine clock frequency f
53 mb90570 series ? block diagram of 8/16-bit up/down counter/timer 1 internal data bus rcr1 reload compare register 1 re-load control circuit up/down count register 1 udcr1 counter control register 1 (ccrl1) ctut cge1 cge0 ucre udcc rlde cgsc pa5/zin1 pin edge/level detection circuit counter clear circuit overflow underflow compare control circuit f pa3/ain1/irq7 pin pin pa4/bin1 carry/borrw (from channel 0) up/down count clock selector counter status register 1 (csr1) count clock cstr cite udie cmpf ovff udff udf1 udf0 cdcf ces1 ces0 cfie cms1 clks cms0 interrupt request #31* interrupt request #32* counter control register 1 (ccrh1) (from channel 1) * : interrupt number f : machine clock frequency m16e prescaler
54 mb90570 series 7. extended i/o serial interface the extended i/o serial interface transfers data using a clock synchronization system having an 8-bit x 1 channel configuration. for data transfer, you can select lsb first/msb first. (1) register configuration ? serial mode control upper status register 0 to 2 (smcsh0 to smcsh2) ? serial mode control lower status register 0 to 2 (smcsl0 to smcsl2) ? serial data register 0 to 2 (sdr0 to sdr2) bit 7 bit 0 address smcsh0: 000049 h smcsh1: 00004d h smcsh2: 00007d h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............. initial value 00000010 b smd2 smd1 smd0 sie sir busy stop strt (smcsl) r/w r/w r/w r/w r/w r r/w r/w bit 15 bit 8 address (smcsh) r/w r/w r/w r/w bit 7 bit 6 bit 5 bit 4 bds mode scoe soe ............ bit 3 bit 2 bit 1 bit 0 smcsl0: 000048 h smcsl1: 00004c h smcsl2: 00007c h initial value - - - - 0000 b bit 15 bit 8 address d6 d7 (disabled) r/w r/w r/w r/w r/w r/w r/w r/w bit 7 bit 6 bit 5 bit 4 d4 d5 d2 d3 d0 d1 ............ bit 3 bit 2 bit 1 bit 0 sdr0: 00004a h sdr1: 00004e h sdr2: 00007e h initial value xxxxxxxx b r/w : readable and writable r : read only :reserved x : undefined
55 mb90570 series (2) block diagram internal data bus pin (msb first) d0 to d7 d7 to d0 (lsb first) transfer direction selection serial data register (sdr) read write shift clock counter p44/sot1 p51/sot2 pin p43/sin1 p50/sin2 pin pin pin p45/sck1 p52/sck2 pin control circuit internal clock 210 smd2 smd1 smd0 sie sir busy stop strt mode bds soe scoe interrupt request #19 (smcs0)* #21 (smcs1)* #23 (smcs2)* *: interrupt number serial mode control status register (smcs) pin p42/sck0 pin p40/sin0 p41/sot0 pin
56 mb90570 series 8. i 2 c interface the i 2 c interface is a serial i/o port supporting inter ic bus operating as master/slave devices on i 2 c bus. the mb90570/a series contains one channel of an i 2 c interface, having the following features. ? master/slave transmission/reception ? arbitration function ? clock synchronization function ? slave address/general call address detection function ? transmission direction detection function ? repeated generation function start condition and detection function ? bus error detection function (1) register configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?i 2 c bus status register (ibsr) bit 15 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (ibcr) ber beie scc mss ack gcaa inte int bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 0 rrrrrrrr r/w r/w r/w r/w r/w r/w r/w r/w bb rsc al lrb trx aas gca fbt (ibsr) initial value 00000000 b address 000068 h address 000069 h initial value 00000000 b bit 15 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (iadr) r/w en cs4 cs3 cs2 cs1 cs0 initial value --0xxxxx b address 00006a h r/w r/w r/w r/w r/w ?i 2 c bus control register (ibcr) ?i 2 c bus clock control register (iccr) a6a5 a4 a3a2a1 a0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 0 r/w r/w r/w r/w r/w r/w r/w (iccr) address 00006b h initial value -xxxxxxx b bit 15 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (disabled) d7 initial value xxxxxxxx b address 00006c h r/w r/w r/w r/w r/w d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w : readable and writable r : read only : reserved x : indeterminate ?i 2 c bus address register (iadr) ?i 2 c bus data register (idar)
57 mb90570 series (2) block diagram internal data bus i 2 c bus control register (ibcr) i 2 c bus status register (ibsr) ber beie scc mss ack gcaa inte int bb rsc al lrb trx aas gca fbt error start master ack enable gc-ack enable interrupt enable transmission complete flag bus busy repeat start last bit transmit/receive slave general call detection of first byte number of interrupt request generated start stop condition generation circuit start stop condition detection circuit interrupt request signal #36* sda line scl line pin pin pa7/scl i 2 c enable idar register slave address comparison circuit iadr register arbitration lost detection circuit clock control block 4 f clock divider 1 (1/5 to 1/8) count clock selector 1 clock divider 2 count clock selector 2 shift clock generation circuit sync 8 i 2 c enable en cs4 cs3 cs2 cs1 cs0 i 2 c bus clock control register (iccr) f : machine clock frequency * : interrupt number pa 6 / s da
58 mb90570 series 9. uart0 (sci), uart1 (sci) uart0 (sci) and uart1 (sci) are general-purpose serial data communication interfaces for performing synchronous or asynchronous communication (start-stop synchronization system). ? data buffer: full-duplex double buffer ? transfer mode: clock synchronized (with start and stop bit) clock asynchronized (start-stop synchronization system) ? baud rate: embedded dedicated baud rate generator external clock input possible internal clock (a clock supplied from 16-bit reload timer 0 can be used.) ? data length: 7 bit to 9 bit selective (without a parity bit) 6 bit to 8 bit selective (with a parity bit) ? signal format: nrz (non return to zero) system ? reception error detection: framing error overrun error parity error (multi-processor mode is supported, enabling setup of any baud rate by an external clock.) ? interrupt request: receive interrupt (receive complete, receive error detection) transmit interrupt (transmission complete) transmit/receive conforms to extended intelligent i/o service (ei 2 os) asynchronization 9615 bps/31250 bps/4808 bps/2404 bps/1202 bps clk synchronization 1 mbps/500 kbps/250 kbps/125 kbps/62.5 kbps } internal machine clock for 6 mhz, 8 mhz, 10 mhz 12 mhz and 16 mhz
59 mb90570 series (1) register configuration ? serial control register 0,1 (scr0, scr1) pen p sbl cl a/d rec rxe txe address 000021 h 000025 h (smr0, smr1) bit 7 bit 0 ............. ? serial mode register 0, 1 (smr0, smr1) md1 md0 cs2 cs1 cs0 resv scke soe address 000020 h 000024 h (scr0, scr1) bit 15 bit 8 ............ ? serial status register 0,1 (ssr0, ssr1) address 000023 h 000027 h ? serial input data register 0,1 (sidr0, sidr1) address 000022 h 000026 h ? serial output data register 0,1 (sodr0, sodr1) address 000022 h 000026 h r/w r/w r/w r/w r/w w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pe ore fre rdrf trde rie tie bit 7 bit 0 ............. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 (sidr0, sidr1/sodr0,sodr1) rr r rrr/wr/w d7 d6 d5 d4 d3 d2 d1 d0 (ssr0, ssr1) bit 15 bit 8 ............ rrrrrr rr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 d7 d6 d5 d4 d3 d2 d1 d0 (ssr0, ssr1) bit 15 bit 8 ............ wwwwww ww bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 md div3 div2 div1 div0 (disabled) bit 15 bit 8 ............ r/w r/w r/w r/w r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ? communications prescaler control register 0,1 (cdcr0, cdcr1) address 000028 h 00002a h initial value 00000100 b initial value 00000000 b initial value 00001 - 00 b initial value xxxxxxxx b initial value xxxxxxxx b initial value 0 - - - 1111 b r/w: readable and writable r : read only w : write only :reserved x : undefined resv: reserved bit
60 mb90570 series (2) block diagram ? uart0 (sci) clock selector dedicated baud rate generator 8/16-bit ppg timer 1 (upper) external clock p42/sck0 pin p40/sin0 receive condition decision circuit smr0 register scr0 register ssr0 register receive clock receive control circuit start bit detection circuit receive bit counter receive parity counter shift register for reception sidr0 sodr0 transmit clock transmit control circuit transmit start circuit transmit bit counter transmit parity counter shift register for transmission receive interrupt signal #39* transmit interrupt signal #40* p41/sot0 start transmission to i 2 c reception error generation signal (to cpu) internal data bus md1 md0 cs2 cs1 cs0 scke soe pen p sbl cl a/d rec rxe txe pe fre rdrf tdre rie tie * : interrupt number control bus reception complete ore pin pin
61 mb90570 series ?uart1 (sci) clock selector dedicated baud rate generator 8/16-bit ppg timer 1 (upper) p45/sck1 pin p43/sin1 receive condition decision circuit smr1 register scr1 register ssr1 register receive clock receive control circuit start bit detection circuit receive bit counter receive parity counter shift register for reception sidr1 sodr1 transmit clock transmit control circuit transmit start circuit transmit bit counter transmit parity counter shift register for transmission receive interrupt signal #37* transmit interrupt signal #38* p44/sot1 start transmission to e i 2 os reception error generation signal (to cpu) internal data bus md1 md0 cs2 cs1 cs0 scke soe pen p sbl cl a/d rec rxe txe pe fre rdrf tdre rie tie * : interrupt number control bus reception complete ore pin pin
62 mb90570 series 10. dtp/external interrupt circuit dtp (data transfer peripheral), which is located between the peripheral circuit outside the device and the f 2 mc-16lx cpu, receives an interrupt request or dma request generated by the external peripheral circuit* for transmission to the f 2 mc-16lx cpu. dtp is used to activate the intelligent i/o service or interrupt processing. as request levels for irq2 to irq7, two types of h and l can be selected for the intelligent i/o service. rising and falling edges as well as h and l can be selected for an external interrupt request. for irq0 and irq1, a request by a level cannot be entered, but both edges can be entered. * : the external peripheral circuit is connected outside the mb90570/a series device. note: irq0 and irq1 cannot be used for the intelligent i/o service and return from an interrupt. (1) register configuration ? dtp/interrupt factor register (eirr) address 000031 h bit 7 bit 0 er7 er6 er5 er4 er3 er2 er1 er0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............ (enir) initial value xxxxxxxx b r/w r/w r/w r/w r/w r/w r/w r/w address 000030 h bit 15 bit 8 en7 en6 en5 en4 en3 en2 en1 en0 (eirr) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ............ r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000 b address low order address 000032 h bit 15 bit 8 lb3 la3 lb2 la2 lb1 la1 lb0 la0 (elvr upper) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ............ r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000 b ? dtp/interrupt enable register (enir) r/w: readable and writable x : undefined address high order address 000033 h lb7 la7 lb6 la6 lb5 la5 lb4 la4 (elvr lower) initial value 00000000 b r/w r/w r/w r/w r/w r/w r/w r/w ? request level setting register (elvr) bit 7 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............
63 mb90570 series (2) block diagram request level setting register (elvr) lb7 la7 lb6 la6 lb5 la5 lb4 la4 lb3 la3 lb2 la2 lb1 la1 lb0 la0 2 222 22 level edge selector 7 level edge selector 5 level edge selector 3 level edge selector 1 level edge selector 6 level edge selector 4 level edge selector 2 level edge selector 0 dtp/external interrupt input detection circuit er7 er0 er6er5er4er3er2er1 en7 en0 en6en5en4en3en2en1 dtp/interrupt factor register (eirr) interrupt request signal #35* #33* #27* #25* #24* #13* dtp/interrupt enable register (enir) 22 internal data bus pin pa3/ain1/irq7 pin pa0/ain0/irq6 pin pb5/irq5 pin pb4/irq4 pin pb3/irq3 pin pb2/irq2 pin pb1/irq1 pin pb0/irq0 *: interrupt number
64 mb90570 series 11. delayed interrupt generation module the delayed interrupt generation module generates interrupts for switching tasks for development on a real- time operating system (realos series). the module can be used to generate softwarewise generates hardware interrupt requests to the cpu and cancel the interrupts. this module does not conform to the extended intelligent i/o service (ei 2 os). (1) register configuration the dirr is the register used to control delay interrupt request generation/cancellation. programming this register with 1 generates a delay interrupt request. programming this register with 0 cancels a delay interrupt request. upon a reset, an interrupt is canceled. the reserved bit area can be programmed with either 0 or 1. for future extension, however, it is recommended that bit set and clear instructions be used to access this register. (2) block diagram ? delayed interrupt factor generation/cancellation register (dirr) address 00009f h bit 7 bit 0 r0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............ (pacsr) r/w initial value -------0 b r/w: readable and writable :reserved note: upon a reset, an interrupt is canceled. delayed interrupt factor generation/ cancellation register (dirr) *: interrupt number s factor r latch r0 internal data bus interrupt request signal #42*
65 mb90570 series 12. 8/10-bit a/d converter the 8/10-bit a/d converter has a function of converting analog voltage input to the analog input pins (input voltage) to digital values (a/d conversion) and has the following features. ? minimum conversion time: 26.3 m s (at machine clock of 16 mhz, including sampling time) ? minimum sampling time: 4 m s/256 m s (at machine clock of 16 mhz) ? compare time: 176/352 machine cycles per channel (176 machine cycles are used for a machine clock below 8 mhz.) ? conversion method: rc successive approximation method with a sample and hold circuit. ? 8-bit or 10-bit resolution ? analog input pins: selectable from eight channels by software single conversion mode: selects and converts one channel. scan conversion mode:converts two or more successive channels. up to eight channels can be programmed. continuous conversion mode: repeatedly converts specified channels. stop conversion mode:stops conversion after completing a conversion for one channel and wait for the next activation (conversion can be started synchronously.) ? interrupt requests can be generated and the extended intelligent i/o service (ei 2 os) can be started after the end of a/d conversion. furthermore, a/d conversion result data can be transferred to the memory, enabling efficient continuous processing. ? when interrupts are enabled, there is no loss of data even in continuous operations because the conversion data protection function is in effect. ? starting factors for conversion: selected from software activation, and external trigger (falling edge).
66 mb90570 series (1) register configuration ? a/d control status register upper digits (adcs2) address 000037 h bit 7 bit 0 busy int inte paus sts1 sts0 strt resv bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............ (adcs1) r/w r/w r/w r/w r/w r/w w r/w address 000036 h bit 15 bit 8 md1 md0 ans2 ans1 ans0 ane2 ane1 ane0 (adcs2) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w ............ r/w: readable and writable r : read only w : write only :reserved x : undefined ? a/d control status register lower digits (adcs1) ? a/d data register upper digits (adcr2) initial value 00000000 b initial value 00000000 b address 000039 h bit 7 bit 0 dsel st1 st0 ct1 xct0 d9 d8 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............ (adcr1) wwwww address 000038 h bit 15 bit 8 d7 d6 d5 d4 d3 d2 d1 d0 (adcr2) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rrrrrrrr ............ ? a/d data register lower digits (adcr1) initial value xxxxxxxx b initial value 00001 -xx b resv: reserved bit
67 mb90570 series (2) block diagram f : machine clock frequency to : 8/16-bit ppg timer channel 1 output * : interrupt number interrupt request #11* clock selector decoder sample hold circuit control circuit 8-bit d/a converter analog channel selector comparator a/d data register (adcr) avrh, avrl av cc av ss pb6/adtg to a/d control status register (adcs) busy int inte paus sts1 sts0 strt da md1 md0 ans2 ans1 ans0 ane2 ane1 ane0 resv st1st0ct1ct0 d9d8d7d6d5d4d3d2d1d0 p87/an7 p86/an6 p85/an5 p84/an4 p83/an3 p82/an2 p81/an1 p80/an0 2 6 f internal data bus
68 mb90570 series 13. 8-bit d/a converter the 8-bit d/a converter, which is based on the r-2r system, supports 8-bit resolution mode. it contains two channels each of which can be controlled in terms of output by the d/a control register. (1) register configuration bit 7 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............ bit 15 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ............ bit 7 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............ bit 15 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ............ ? d/a converter data register ch.0 (dadr0) address 00003a h da17 da16 da15 da14 da13 da12 da11 da10 (dadr0) r/w r/w r/w r/w r/w r/w r/w r/w address 00003b h da07 da06 da05 da04 da03 da02 da01 da00 (dadr1) r/w r/w r/w r/w r/w r/w r/w r/w r/w: readable and writable :reserved x : undefined ? d/a converter data register ch.1 (dadr1) ? d/a control register 0 (dacr0) initial value xxxxxxxx b initial value xxxxxxxx b address 00003c h address 00003d h ? d/a control register 1 (dacr1) initial value -------0 b initial value -------0 b dae0 (dacr1) dae1 (dacr0) r/w r/w
69 mb90570 series (2) block diagram da17 internal data bus internal data bus d/a converter data register ch.1 (dadr1) d/a converter data register ch.0 (dadr0) da16 da15 da14 da13 da12 da11 da10 da07 da06 da05 da04 da03 da02 da01 da00 d/a converter 1 d/a converter 0 da17 da16 da15 da14 da13 da12 da11 da10 da07 da06 da05 da04 da03 da02 da01 da00 dvrh dvrl 2r r 2r r 2r r 2r r 2r r 2r r 2r r 2r 2r dv ss 2r r 2r r 2r r 2r r 2r r 2r r 2r r dv ss pin p74/da1 pin p73/da0 standby control d/a control register 1 (dacr1) standby control d/a control register 0 (dacr0) dae1 dae0 2r 2r
70 mb90570 series 14. clock timer the clock timer control register (wtc) controls operation of the clock timer, and time for an interval interrupt. (1) register configuration (2) block diagram ? clock timer control register (wtc) address 0000aa h bit 15 bit 8 wdcs sce wtie wtof wtr wtc2 wtc1 wtc0 (disabled) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r r/w r/w r/w r r/w r/w ............ r/w: readable and writable r : read only x : undefined initial value 1x000000 b clock counter lclk power-on reset shift to a hardware standby shift to stop mode counter clear circuit interval timer selector clock timer interrupt request #22* clock timer control register (wtc) wdcs to sub-clock oscillation stabilization time controller to watchdog timer 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 of of of of of of of sce wtie wtof wtr wtc2 wtc1 wtc0 * : interrupt number of : overflow lclk : oscillation sub-clock frequency
71 mb90570 series 15. chip select output this module generates a chip select signal for facilitating a memory and i/o unit, and is provided with eight chip select output pins. when access to an address is detected with a hardware-set area set for each pin register, a select signal is output from the pin. (1) register configuration ? chip selection control register 1, 3, 5, 7 (cscr1, cscr3, cscr5, cscr7) address cscr1: 000081 h cscr3: 000083 h cscr5: 000085 h cscr7: 000087 h bit 7 bit 0 actl opel csa1 csa0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............ (cscr0, cscr2, cscr4, cscr6) r/w r/w r/w r/w bit 15 bit 8 (cscr1, cscr3, cscr5, cscr7) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ............ r/w: readable and writable :reserved ? chip selection control register 0, 2, 4, 6 (cscr0, cscr2, cscr4, cscr6) initial value ---- 0000 b initial value ---- 0000 b r/w r/w r/w r/w actl opel csa1 csa0 address cscr0: 000080 h cscr2: 000082 h cscr4: 000084 h cscr6: 000086 h
72 mb90570 series (2) block diagram a23 a22 a17 a16 address decoder a15 a14 a01 a00 2 address decoder decode signal decode program area chip selection control register 0 (cscr0) p90/cs0 (program rom area application) p91/cs1 p92/cs2 p93/cs3 p94/cs4 p95/cs5 p96/cs6 p97/cs7 selector selector selector selector selector selector selector selector select and set select and set select and set select and set select and set select and set select and set chip selection control register 1 (cscr1) chip selection control register 2 (cscr2) chip selection control register 3 (cscr3) chip selection control register 4 (cscr4) chip selection control register 5 (cscr5) chip selection control register 6 (cscr6) chip selection control register 7 (cscr7) from address (cpu) select and set
73 mb90570 series (3) decode address spaces pin name csa decode space number of area bytes remarks 10 cs0 0 0 f00000 h to ffffff h 1 mbyte becomes active when the program rom area or the program vector is fetched. 0 1 f80000 h to ffffff h 512 kbyte 1 0 fe0000 h to ffffff h 128 kbyte 11 disabled cs1 0 0 e00000 h to efffff h 1 mbyte adapted to the data rom and ram areas, and external circuit connection applications. 0 1 f00000 h to f7ffff h 512 kbyte 1 0 fc0000 h to fdffff h 128 kbyte 1 1 68ff80 h to 68ffff h 128 byte cs2 0 0 003000 h to 003fff h 4 kbyte adapted to the data rom and ram areas, and external circuit connection applications. 0 1 fa0000 h to fbffff h 128 kbyte 1 0 68ff80 h to 68ffff h 128 byte 1 1 68ff00 h to 68ff7f h 128 byte cs3 0 0 f80000 h to f9ffff h 128 kbyte adapted to the data rom and ram areas, and external circuit connection applications. 0 1 68ff00 h to 68ff7f h 128 byte 1 0 68fe80 h to 68feff h 128 byte 11 disabled cs4 0 0 002800 h to 002fff h 2 kbyte adapted to the data rom and ram areas, and external circuit connection applications. 0 1 68fe80 h to 68feff h 128 byte 10 disabled 11 disabled cs5 0 0 68ff80 h to 68ffff h 128 byte adapted to the data rom and ram areas, and external circuit connection applications. 01 disabled 10 disabled 11 disabled cs6 0 0 68ff00 h to 68ff7f h 128 byte adapted to the data rom and ram areas, and external circuit connection applications. 01 disabled 10 disabled 11 disabled cs7 disabled disabled
74 mb90570 series 16. communications prescaler register this register controls machine clock division. output from the communications prescaler register is used for uart0 (sci), uart1 (sci), and extended i/o serial interface. the communications prescaler register is so designed that a constant baud rate may be acquired for various machine clocks. (1) register configuration ? communications prescaler control register 0,1 (cdcr0, cdcr1) address bit 15 bit 8 md div3 div2 div1 div0 (disabled) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w ............ r/w: readable and writable :reserved initial value 0 - - - 1111 b 000028 h 00002a h
75 mb90570 series 17. address match detection function when the address is equal to a value set in the address detection register, the instruction code loaded into the cpu is replaced forcibly with the int9 instruction code (01h). as a result, when the cpu executes a set instruction, the int9 instruction is executed. processing by the int#9 interrupt routine allows the program patching function to be implemented. two address detection registers are supported. an interrupt enable bit is prepared for each register. if the value set in the address detection register matches an address and if the interrupt enable bit is set at 1, the instruction code loaded into the cpu is replaced forcibly with the int9 instruction code. (1) register configuration ? program address detection register 0 to 2 (padr0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value xxxxxxxx b r/w: readable and writable x : undefined address padr0 (low order address): 001ff0 h r/w r/w r/w r/w r/w r/w r/w r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value xxxxxxxx b address padr0 (middle order address): 001ff1 h r/w r/w r/w r/w r/w r/w r/w r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value xxxxxxxx b address padr0 (high order address): 001ff2 h r/w r/w r/w r/w r/w r/w r/w r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value xxxxxxxx b address padr1 (low order address): 001ff3 h r/w r/w r/w r/w r/w r/w r/w r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value xxxxxxxx b address padr1 (middle order address): 001ff4 h r/w r/w r/w r/w r/w r/w r/w r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value xxxxxxxx b address padr1 (high order address): 001ff5 h r/w r/w r/w r/w r/w r/w r/w r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 00000000 b address 00009e h r/w r/w r/w r/w r/w r/w r/w r/w ? program address detection register 3 to 5 (padr1) ? program address detection control status register (pacsr) resv resv resv resv ad1e resv ad0e resv resv: reserved bit
76 mb90570 series (2) block diagram internal data bus address latch enable bit f 2 mc-16lx cpu core address detection register compare int9 instruction
77 mb90570 series 18. rom mirroring function selection module the rom mirroring function selection module can select what the ff bank allocated the rom sees through the 00 bank according to register settings. (1) register configuration note: do not access this register during operation at addresses 004000 h to 00ffff h . (2) block diagram ? rom mirroring function selection register (romm) address 00006f h bit 7 bit 0 mi bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............ (disabled) w : write only :reserved initial value -------1 b w rom mirroring function selection register (romm) address area ff bank 00 bank rom data internal data bus address
78 mb90570 series 19. low-power consumption (standby) mode the f 2 mc-16lx has the following cpu operating mode configured by selection of an operating clock and clock operation control. ?clock mode pll clock mode : a mode in which the cpu and peripheral equipment are driven by pll-multiplied oscillation clock (hclk). main clock mode: a mode in which the cpu and peripheral equipment are driven by divided-by-2 of the oscillation clock (hclk). the pll multiplication circuits stops in the main clock mode. ? cpu intermittent operation mode the cpu intermittent operation mode is a mode for reducing power consumption by operating the cpu intermittently while external bus and peripheral functions are operated at a high-speed. ? hardware standby mode the hardware standby mode is a mode for reducing power consumption by stopping clock supply to the cpu by the low-power consumption control circuit, stopping clock supplies to the cpu and peripheral functions (timebase timer mode), and stopping oscillation clock (stop mode, hardware standby mode). of these modes, modes other than the pll clock mode are power consumption modes. (1) register configuration ? clock select register (ckscr) address 0000a1 h bit 7 bit 0 scm mcm ws1 ws0 scs mcs cs1 cs0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ............ (lpmcr) r r r/w r/w r/w r/w r/w r/w address 0000a0 h bit 15 bit 8 stp slp spl rst tmd cg1 cg0 ssr (ckscr) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w w r/w w r/w w r/w r/w ............ r/w: readable and writable r : read only w : write only ? low-power consumption mode control register (lpmcr) initial value 00011000 b initial value 11111100 b
79 mb90570 series (2) block diagram stp standby control circuit slp spl rst tmd cg1 cg0 ssr low-power consumption mode control register (lpmcr) hardware standby reset interrupt sq r sq r sq r sq r 2 2 2 cpu intermittent operation cycle selector cpu clock control circuit peripheral clock control circuit cpu operation clock peripheral function operation clock clock mode sleep signal stop signal machine clock clock selector pll multiplication circuit clock select register (ckscr) scm mcm ws1 ws0 scs mcs cs1 cs0 timebase timer to watchdog timer clock timer sub-clock oscillator oscillation sub-clock oscillation clock clock oscillator main clock 1/2 1/2048 1/4 1/4 1/8 1/1024 1/8 1/2 1/2 oscillation stabilization time selector pin x0 pin x1 pin x0a pin x1a s: set r: reset q: output
80 mb90570 series n electrical characteristics 1. absolute maximum ratings (av ss = v ss = 0.0 v) *1: av cc , avrh, avrl, and dvrh shall never exceed v cc . avrl shall never exceed avrh. *2: v i and v o shall never exceed v cc + 0.3 v. *3: the maximum output current is a peak value for a corresponding pin. *4: average output current is an average current value observed for a 100 ms period for a corresponding pin. *5: total average current is an average current value observed for a 100 ms period for all corresponding pins. note: average output current = operating operating efficiency warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol value unit remarks min. max. power supply voltage v cc v ss C 0.3 v ss + 6.0 v av cc v ss C 0.3 v ss + 6.0 v *1 avrh, avrl v ss C 0.3 v ss + 6.0 v *1 dvrh v ss C 0.3 v ss + 6.0 v *1 input voltage v i v ss C 0.3 v ss + 6.0 v *2 output voltage v o v ss C 0.3 v ss + 6.0 v *2 l level maximum output current i ol ? 15 ma *3 l level average output current i olav ? 4ma*4 l level total maximum output current s i ol ? 100 ma l level total average output current s i olav ? 50 ma *5 h level maximum output current i oh ? C15 ma *3 h level average output current i ohav ? C4 ma *4 h level total maximum output current s i oh ? C100 ma h level total average output current s i ohav ? C50 ma *5 power consumption p d ? 300 mw mb90573/4 mb90v570/a ? 500 mw MB90574C ? 800 mw mb90f574/a operating temperature t a C40 +85 c storage temperature tstg C55 +150 c
81 mb90570 series 2. recommended operating conditions (av ss = v ss = 0.0 v) * : use a ceramic capacitor or a capacitor with equivalent frequency characteristics. the smoothing capacitor to be connected to the v cc pin must have a capacitance value higher than c s . warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit remarks min. max. power supply voltage v cc 3.0 5.5 v normal operation (mb90574/c) v cc 4.5 5.5 v normal operation (mb90f574/a) v cc 3.0 5.5 v retains status at the time of operation stop smoothing capacitor c s 0.1 1.0 m f* operating temperature t a C40 +85 c ? c pin connection circuit c s c
82 mb90570 series 3. dc characteristics (av cc = v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) (continued) parameter symbol pin name condition value unit remarks min. typ. max. h level input voltage v ihs cmos hysteresis input pin v cc = 3.0 v to 5.5 v (mb90573) (mb90574) v cc = 4.5 v to 5.5 v (mb90f574) 0.8 v cc v cc + 0.3 v v ihm md pin input v cc C 0.3 v cc + 0.3 v l level input voltage v ils cmos hysteresis input pin v ss C 0.3 0.2 v cc v v ilm md pin input v ss C 0.3 v ss + 0.3 v h level output voltage v oh other than pa6 and pa7 v cc = 4.5 v i oh = C2.0 ma v cc C 0.5 v l level output voltage v ol all output pins v cc = 4.5 v i ol = 2.0 ma 0.4v open-drain output leakage current i leak pa 6 , pa 7 0 . 1 5 m a input leakage current i il other than pa6 and pa7 v cc = 5.5 v v ss < v i < v cc C5 5 m a pull-up resistance r up p00 to p07, p10 to p17, p60 to p67, rst , md0, md1 15 30 100 k w pull-down resistance r down md0 to md2 15 30 100 k w power supply current* i cc v cc internal operation at 16 mhz v cc at 5.0 v normal operation 3040ma mb90574 i cc v cc 85 130 ma mb90f574/a i cc v cc 5080ma MB90574C i cc v cc internal operation at 16 mhz v cc at 5.0 v a/d converter operation 3545ma mb90574 i cc v cc 90 140 ma mb90f574/a i cc v cc 5585ma MB90574C i cc v cc internal operation at 16 mhz v cc at 5.0 v d/a converter operation 4050ma mb90574 i cc v cc 95 145 ma mb90f574/a i cc v cc 6585ma MB90574C
83 mb90570 series (continued) (av cc = v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : the current value is preliminary value and may be subject to change for enhanced characteristics without previous notice. parameter symbol pin name condition value unit remarks min. typ. max. power supply current* i cc v cc when data written in flash mode programming of erasing 95 140 ma mb90f574/a i ccs v cc internal operation at 16 mhz v cc = 5.0 v in sleep mode 7 12 ma mb90574 i ccs v cc 5 10 ma mb90f574/a i ccs v cc 15 20 ma MB90574C i ccl v cc internal operation at 8 khz v cc = 5.0 v t a = +25 c subsystem operation 0.1 1.0 ma mb90574 i ccl v cc 4 7 ma mb90f574/a i ccl v cc 0.03 1 ma MB90574C i ccls v cc internal operation at 8 khz v cc = 5.0 v t a = +25 c in subsleep mode 30 50 ma mb90574 i ccls v cc 0.1 1 ma mb90f574/a i ccls v cc 1050 m a MB90574C i cct v cc internal operation at 8 khz v cc = 5.0 v t a = +25 c in clock mode 1530 m a mb90574 i cct v cc 3050 m a mb90f574/a i cct v cc 1.030 m a MB90574C i cch v cc t a = +25 c in stop mode 520 m a mb90574 i cch v cc 0.110 m a mb90f574/a MB90574C input capacitance c in other than av cc , av ss , v cc , v ss 10 80 pf
84 mb90570 series 4. ac characteristics (1) reset, hardware standby input timing (av cc = v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for t cp (internal operating clock cycle time), refer to (3) clock timings. parameter symbol pin name condition value unit remarks min. max. reset input time t rstl rst 4 t cp *ns hardware standby input time t hstl hst 4 t cp *ns 0.2 v cc t rstl , t hstl rst hst 0.2 v cc ? measurement conditions for ac characteristics pin c l c l is a load capacitance connected to a pin under test. capacitors of c l = 30 pf must be connected to clk and ale pins, while c l of 80 pf must be connected to address data bus (ad15 to ad00), rd , wrl , and wrh pins.
85 mb90570 series (2) specification for power-on reset (av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : v cc must be kept lower than 0.2 v before power-on. notes: ? the above ratings are values for causing a power-on reset. ? there are internal registers which can be initialized only by a power-on reset. apply power according to this rating to ensure initialization of the registers. parameter symbol pin name condition value unit remarks min. max. power supply rising time t r v cc 0.05 30 ms * power supply cut-off time t off v cc 4ms due to repeated operations v cc t off 0.2 v 2.7 v 0.2 v 0.2 v t r v ss sudden changes in the power supply voltage may cause a power-on reset. to change the power supply voltage while the device is in operation, it is recommended to raise the voltage smoothly to suppress fluctuations as shown below. in this case, change the supply voltage with the pll clock not used. if the voltage drop is 1 mv or fewer per second, however, you can use the pll clock. v cc 3.0 v it is recommended to keep the rising speed of the supply voltage at 50 mv/ms or slower.
86 mb90570 series (3) clock timings (av cc = v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : the frequency fluctuation rate is the maximum deviation rate of the preset center frequency when the multiplied pll signal is locked. the pll frequency deviation changes periodically from the preset frequency (about clk (1cyc to 50 cyc), thus minimizing the chance of worst values to be repeated (errors are minimal and negligible for pulses with long intervals). parameter symbol pin name condition value unit remarks min. typ. max. clock frequency f c x0, x1 316mhz f cl x0a, x1a 32.768 khz clock cycle time t hcyl x0, x1 62.5 333 ns t lcyl x0a, x1a 30.5 m s input clock pulse width p wh , p wl x0 10 ns recommend duty ratio of 30% to 70% p wlh , p wll x0a 15.2 m s input clock rising/falling time t cr , t cf x0, x0a 5 ns external clock operation internal operating clock frequency f cp 1.516mhz main clock operation f lcp 8.192khz subclock operation internal operating clock cycle time t cp 62.5 333 ns external clock operation t lcp 122.1 m s subclock operation frequency fluctuation rate locked d f 5%* | a | f o center frequency + C + a f o C a d f = 100 (%)
87 mb90570 series ? x0, x1 clock timing p wh 0.2 v cc 0.8 v cc 0.8 v cc 0.8 v cc p wl t cf t cr t hcyl 0.2 v cc ? x0a, x1a clock timing p wlh 0.2 v cc 0.8 v cc 0.8 v cc 0.8 v cc p wll t cf t cr t lcyl 0.2 v cc x0 x0a 5.5 4.5 3.3 3.0 16 12 9 8 4 34 8 16 1.5 3 8 12 16 6 12 6 2 3 1.5 ? pll operation guarantee range relationship between internal operating clock frequency and power supply voltage (mhz) internal clock f cp p o w e r s u p p l y v o l t a g e v c c (v) operation guarantee range (mb90f574/a) pll operation guarantee range relationship between oscillating frequency, internal operating clock frequency, and power supply voltage (mhz) multiplied- by-4 multiplied- by-3 not multiplied multiplied-by-2 multiplied-by-1 i n t e r n a l c l o c k f c p oscillation clock f c (mhz) operation guarantee range MB90574C operation guarantee range mb90v570/a operation guarantee range mb90573/4
88 mb90570 series the ac ratings are measured for the following measurement reference voltages. (4) recommended resonator manufacturers ? input signal waveform ? output signal waveform 0.8 v cc 0.2 v cc hystheresis input pin 0.7 v cc 0.3 v cc pins other than hystheresis input/md input hystheresis input pin 2.4 v cc 0.8 v cc ? mask rom product (mb90574) (continued) resonator manufacturer* resonator frequency (mhz) c 1 (pf) c 1 (pf) r murata mfg. co., ltd. csa2.00mg040 2.00 100 100 no required csa4.00mg040 4.00 100 100 no required csa8.00mtz 8.00 30 30 no required csa16.00mxz040 16.00 15 15 no required csa32.00mxz040 32.00 5 5 no required tdk corporation ccr3.52mc3 to ccr6.96mc3 3.52 to 6.96 built-in built-in no required ccr7.0mc5 to ccr12.0mc5 7.00 to 12.00 built-in built-in no required ccr20.0msc6 to ccr32.0msc6 20.00 to 32.00 built-in built-in no required ? sample application of ceramic resonator x0 x1 r c 1 c 2 *
89 mb90570 series (continued) (5) clock output timing (av cc = v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) parameter symbol pin name condition value unit remarks min. max. cycle time t cyc clk 62.5 ns clk - ? clk t chcl clk 20 ns ? flash product (mb90f574) inquiry: murata mfg. co., ltd. ? murata electronics north america, inc.: tel 1-404-436-1300 ? murata europe management gmbh: tel 49-911-66870 ? murata electronics singapore (pte.): tel 65-758-4233 tdk corporation ? tdk corporation of america chicago regional office: tel 1-708-803-6100 ? tdk electronics europe gmbh components division: tel 49-2102-9450 ? tdk singapore (pte) ltd.: tel 65-273-5022 ? tdk hongkong co., ltd.: tel: 852-736-2238 ? korea branch, tdk corporation: tel 82-2-554-6636 resonator manufacturer* resonator frequency (mhz) c 1 (pf) c 2 (pf) r murata mfg. co., ltd. csa2.00mg040 2.00 100 100 no required csa4.00mg040 4.00 100 100 no required csa8.00mtz 8.00 30 30 no required csa16.00mxz040 16.00 15 15 no required csa32.00mxz040 32.00 5 5 no required tdk corporation ccr3.52mc3 to ccr6.96mc3 3.52 to 6.96 built-in built-in no required ccr7.0mc5 to ccr12.0mc5 7.00 to 12.00 built-in built-in no required ccr20.0msc6 to ccr32.0msc6 20.00 to 32.00 built-in built-in no required 2.4 v 0.8 v t cyc t chcl 2.4 v clk
90 mb90570 series (6) bus read timing (av cc = v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for t cp (internal operating clock cycle time), refer to (3) clock timings. parameter symbol pin name condition value unit remarks min. max. ale pulse width t lhll ale 1 t cp */2 C 20 ns effective address ? ale time t avll ale, a23 to a16, ad15 to ad00 1 t cp */2 C 20 ns ale ? address effective time t llax ale, ad15 to ad00 1 t cp */2 C 15 ns effective address ? rd time t avrl rd , a23 to a16, ad15 to ad00 1 t cp * C 15 ns effective address ? valid data input t avdv a23 to a16, ad15 to ad00 5 t cp */2 C 60 ns rd pulse width t rlrh rd 3 t cp */2 C 20 ns rd ? valid data input t rldv rd , ad15 to ad00 3 t cp */2 C 60 ns rd - ? data hold time t rhdx rd , ad15 to ad00 0ns rd - ? ale - time t rhlh ale, rd 1 t cp */2 C 15 ns rd - ? address effective time t rhax ale, a23 to a16 1 t cp */2 C 10 ns effective address ? clk - time t avch clk, a23 to a16, ad15 to ad00 1 t cp */2 C 20 ns rd ? clk - time t rlch clk, rd 1 t cp */2 C 20 ns ale ? rd time t alrl ale, rd 1 t cp */2 C 15 ns
91 mb90570 series clk 2.4 v t avch ale rd ad23 to ad16 0.8 v cc 0.2 v cc ad15 to ad00 address read data 2.4 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 0.8 v cc 0.2 v cc t rlch t rhlh t lhll t avll t llax t rlrh t avrl t rldv t rhax t avdv t rhdx 2.4 v
92 mb90570 series (7) bus write timing (av cc = v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for t cp (internal operating clock cycle time), refer to (3) clock timings. parameter symbol pin name condition value unit remarks min. max. effective address ? wr time t avwl wrl , wrh , a23 to a16, ad15 to ad00 1 t cp C 15 ns wr pulse width t wlwh wrl , wrh 3 t cp */2 C 20 ns write data ? wr - time t dvwh wrl , wrh , ad15 to ad00 3 t cp */2 C 20 ns wr - ? data hold time t whdx wrl , wrh , ad15 to ad00 20 ns wr - ? address effective time t whax wrl , wrh , a23 to a16 1 t cp */2 C 10 ns wr - ? ale - time t whlh ale, wrl 1 t cp */2 C 15 ns wr ? clk - time t wlch clk, wrh 1 t cp */2 C 20 ns clk 2.4 v t wlch ale wrl , wrh a23 to a16 2.4 v 0.8 v ad15 to ad00 address write data t whlh t avwl t wlwh t dvwh t whdx t whax 2.4 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 2.4 v 0.8 v 0.8 v
93 mb90570 series (8) ready input timing (av cc = v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) note: use the automatic ready function when the setup time for the rising edge of the rdy signal is not sufficient. (9) hold timing (av cc = v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for t cp (internal operating clock cycle time), refer to (3) clock timings. note: more than 1 machine cycle is needed before hak changes after hrq pin is fetched. parameter symbol pin name condition value unit remarks min. max. rdy setup time t ryhs rdy 45 ns rdy hold time t ryhh rdy 0 ns parameter symbol pin name condition value unit remarks min. max. pins in floating status ? hak time t xhal hak 30 1 t cp *ns hak - ? pin valid time t hahv hak 1 t cp *2 t cp *ns clk 2.4 v 0.8 v cc t ryhs ale rd /wrl , rd /wrh rdy (wait inserted) rdy (wait not inserted) 2.4 v t ryhs 0.2 v cc 0.2 v cc 0.8 v cc t ryhh pins hak high impedance t xhal 2.4 v 0.8 v 2.4 v 0.8 v t hahv 0.8 v 2.4 v
94 mb90570 series (10) uart0 (sci), uart1 (sci) timing (av cc = v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for t cp (internal operating clock cycle time), refer to (3) clock timings. notes: ? these are ac ratings in the clk synchronous mode. ?c l is the load capacitance value connected to pins while testing. parameter symbol pin name condition value unit remarks min. max. serial clock cycle time t scyc sck0 to sck4 internal shift clock mode c l = 80 pf + 1 ttl for an output pin 8 t cp *ns sck ? sot delay time t slov sck0 to sck4, sot0 to sot4 C 80 80 ns valid sin ? sck - t ivsh sck0 to sck4, sin0 to sin4 100 ns sck - ? valid sin hold time t shix sck0 to sck4, sin0 to sin4 60 ns serial clock h pulse width t shsl sck0 to sck4 external shift clock mode c l = 80 pf + 1 ttl for an output pin 4 t cp *ns serial clock l pulse width t slsh sck0 to sck4 4 t cp *ns sck ? sot delay time t slov sck0 to sck4, sot0 to sot4 150 ns valid sin ? sck - t ivsh sck0 to sck4, sin0 to sin4 60 ns sck - ? valid sin hold time t shix sck0 to sck4, sin0 to sin4 60 ns
95 mb90570 series ? internal shift clock mode ? external shift clock mode sck0 to sck4 2.4 v 0.8 v sot0 to sot4 sin0 to sin4 sck0 to sck4 sot0 to sot4 sin0 to sin4 0.8 v 2.4 v 0.2 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc 0.2 v cc 0.8 v cc t scyc t ivsh t shix t slov t slsh t shsl t ivsh t shix t slov
96 mb90570 series (11) timer input timing (av cc = v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for t cp (internal operating clock cycle time), refer to (3) clock timings. (12) timer output timing (av cc = v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) parameter symbol pin name condition value unit remarks min. max. input pulse width t tiwh , t tiwl in0, in1 4 t cp *ns parameter symbol pin name condition value unit remarks min. max. clk - ? t out transition time t to out0 to out3, ppg0, ppg1 30ns t tiwh 0.8 v cc 0.2 v cc t tiwl 0.8 v cc 0.2 v cc in0 , in1 clk t to 2.4 v t out 2.4 v 0.8 v
97 mb90570 series (13) trigger input timing (av cc = v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for t cp (internal operating clock cycle time), refer to (3) clock timings. parameter symbol pin name condition value unit remarks min. max. input pulse width t trgl irq0 to irq5, adtg, in0, in1 5 t cp *ns 0.2 v cc 0.8 v cc t trgh 0.8 v cc 0.2 v cc irq0 to irq5 adtg, in0, in1 t trgl
98 mb90570 series (14) chip select output timing (av cc = v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for t cp (internal operating clock cycle time), refer to (3) clock timings. parameter symbol pin name condition value unit remarks min. max. valid chip select output ? valid data input time t svdv cs0 to cs7, ad15 to ad00 5 t cp */2 C 60 ns rd - ? chip select output effective time t rhsv rd , cs0 to cs7 1 t cp */2 C 10 ns wr - ? chip select output effective time t whsv cs0 to cs7, wrl , wrh 1 t cp */2 C 10 ns valid chip select output ? clk - time t svch clk, cs0 to cs7 1 t cp */2 C 20 ns clk 2.4 v read data 2.4 v 0.8 v t svch 2.4 v 2.4 v 2.4 v write data 0.8 v a23 to a16 cs0 to cs7 ad15 to ad00 wrl , wrh ad15 to ad00 rd t rhsv t svdv t whsv
99 mb90570 series (15) i 2 c timing (av cc = v cc = 2.7 v to 5.5 v, av ss = v ss = 0.0 v, t a = C40 c to +85 c) notes: ? m and n in the above table represent the values of shift clock frequency setting bits (cs4-cs0) in the clock control register iccr. for details, refer to the register description in the hardware manual. ?t dosuo represents the minimum value when the interrupt period is equal to or greater than the scl l width. ? the sda and scl output values indicate that rise time is 0 ns. parameter symbol pin name condition value unit remarks min. max. internal clock cycle time t cp 62.5 666 ns all products start condition output t stao sda,scl t cp m n/2-20 t cp m n/2+20 ns only as master stop condition output t stoo t cp (m n/ 2+4)-20 t cp (m n/ 2+4)+20 ns start condition detection t stai 3t cp +40 ns only as slave stop condition detection t stoi 3t cp +40 ns scl output l width t lowo scl t cp m n/2-20 t cp m n/2+20 ns only as master scl output h width t higho t cp (m n/ 2+4)-20 t cp (m n/ 2+4)+20 ns sda output delay time t doo sda,scl 2t cp -20 2t cp +20 ns setup after sda output interrupt period t dosuo 4t cp -20 ns scl input l width t lowi scl 3t cp +40 ns scl input h width t highi t cp +40 ns sda input setup time t sui sda,scl 40 ns sda input hold time t hoi 0ns
100 mb90570 series scl sda scl sda t stao t doo t doo t dosuo t sui t sui t hoi t doo t doo t dosuo t stoi t hoi 0.2 v cc 0.2 v cc 0.2 v cc 0.2 v cc 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 0.8 v cc 0.8 v cc 0.8 v cc 0.8 v cc 0.8 v cc 0.8 v cc 1 67 8 9 89 ack ack t lowo t higho t highi t lowi ?i 2 c interface [data transmitter (master/slave)] ?i 2 c interface [data receiver (master/slave)]
101 mb90570 series (16) pulse width on external interrupt pin at return from stop mode * : for t cp (internal operating clock cycle time), refer to (3) clock timings. (av cc = v cc = 2.7 v to 5.5 v, av ss = v ss = 0.0 v, t a = C40 c to +85 c) parameter symbol pin name condition value unit remarks min. max. input pulse width t irqwh t irqwl irq2 to irq7 ? 6t cp ? ns irq2 ~ irq7 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t irqwh t irqwl irq2 ~ irq7 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t irqwh t irqwl
102 mb90570 series 5. a/d converter electrical characteristics (av cc = v cc = 2.7 v to 5.5 v, av ss = v ss = 0.0 v, 2.7 v avrh C avrl, t a = C40 c to +85 c) parameter symbol pin name condition value unit min. typ. max. resolution 8/10bit total error 5.0 lsb non-linear error 2.5 lsb differential linearity error 1.9 lsb zero transition voltage v ot an0 to an7 C3.5 lsb +0.5 lsb +4.5 lsb mv full-scale transition voltage v fst an0 to an7 avrh C6.5 lsb avrh C1.5 lsb avrh +1.5 lsb mv conversion time v cc = 5.0 v 10% at machine clock of 16 mhz 352t cp m s sampling period v cc = 5.0 v 10% at machine clock of 6 mhz 64t cp m s analog port input current i ain an0 to an7 10 m a analog input voltage v ain an0 to an7 avrl avrh v reference voltage avrh avrl +2.7 av cc v avrl 0 avrh C2.7 v power supply current i a av cc 5ma i ah av cc cpu stopped and 8/10-bit a/d converter not in operation (v cc = av cc = avrh = 5.0 v) 5 m a reference voltage supply current i r avrh 400 m a i rh avrh cpu stopped and 8/10-bit a/d converter not in operation (v cc = av cc = avrh = 5.0 v) 5 m a offset between channels an0 to an7 4lsb
103 mb90570 series 6. a/d converter glossary resolution: analog changes that are identifiable with the a/d converter linearity error: the deviation of the straight line connecting the zero transition point (00 0000 0000 ? 00 0000 0001) with the full-scale transition point (11 1111 1110 ? 11 1111 1111) from actual conversion characteristics differential linearity error: the deviation of input voltage needed to change the output code by 1 lsb from the theoretical value total error: the total error is defined as a difference between the actual value and the theoretical value, which includes zero-transition error/full-scale transition error and linearity error. (continued) total error 3ff 3fe 3fd 004 003 002 001 analog input avrl avrh actual conversion value d i g i t a l o u t p u t v nt (measured value) 0.5 lsb actual conversion characteristics theoretical characteristics 0.5 lsb {1 lsb (n C 1) + 0.5 lsb} [v] avrh C avrl 1024 1 lsb = (theoretical value) v ot (theoretical value) = avrl + 0.5 lsb[v] v fst (theoretical value) = avrh C 1.5 lsb[v] total error for digital output n [lsb] v nt C {1 lsb (n C 1) + 0.5 lsb} 1 lsb = v nt : voltage at a transition of digital output from (n C 1) to n
104 mb90570 series (continued) 7. notes on using a/d converter select the output impedance value for the external circuit of analog input according to the following conditions. output impedance values of the external circuit of 7 k w or lower are recommended. when capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor value is recommended to minimized the effect of voltage distribution between the external capacitor and internal capacitor. when the output impedance of the external circuit is too high, the sampling period for analog voltages may not be sufficient (sampling period = 4.00 m s @machine clock of 16 mhz). ?error the smaller the | avrh C avrl |, the greater the error would become relatively. linearity error n + 1 n n C 1 n C 2 3ff 3fe 3fd 004 003 002 001 analog input avrl avrh analog input avrl avrh actual conversion characteristics v ot (measured value) v fst (measured value) actual conversion value v nt {1 lsb (n C 1)+ v ot } theoretical characteristics d i g i t a l o u t p u t d i g i t a l o u t p u t differential linearity error theoretical characteristics v (n + 1)t (measured value) actual conversion value v nt (measured actual conversion value linearity error of digital output n v ot: voltage at transition of digital output from 000 h to 001 h v fst : voltage at transition of digital output from 3fe h to 3ff h [lsb] v nt C {1 lsb (n C 1) + v ot } 1 lsb = [v] v fst C v ot 1022 = 1 lsb C 1 lsb [lsb] v (n + 1)t C v nt 1 lsb = differential linearity error of digital n ? equipment of analog input circuit model note: listed values must be considered as standards. comparator analog input c 0 c 1 mb90573/4, mb90v570/a r @ 1.5 k w , c @ 30 pf mb90f574/a r @ 3.0 k w , c @ 65 pf MB90574C
105 mb90570 series 8. d/a converter electrical characteristics (av cc = v cc = dv cc = 5.0 v 10%, av ss = v ss = dv ss = 0.0 v, t a = C40 c to +85 c) parameter symbol pin name value unit remarks min. typ. max. resolution 8 bit differential linearity error 0.9 lsb absolute accuracy 1.2 % linearity error 1.5 lsb conversion time 10 20 m s load capacitance: 20 pf analog reference voltage dv cc v ss + 3.0 av cc v reference voltage supply current i dvr dv cc 120 300 m a conversion under no load i dvrs dv cc 10 m a in sleep mode analog output impedance 20k w
106 mb90570 series n example characteristics (1) power supply current (mb90574 ) i cc - v cc fc = 16 mhz i cc (ma) 35 30 25 20 15 10 5 3.0 4.0 5.0 6.0 v cc (v) t a = +25 c fc = 12.5 mhz fc = 10 mhz fc = 8 mhz fc = 5 mhz fc = 4 mhz fc = 2 mhz i cc - t a fc = 16 mhz i cc (ma) 35 30 25 20 15 10 5 C20 +10 +40 +70 t a ( c) v cc = 5.0 v fc = 12.5 mhz fc = 10 mhz fc = 8 mhz fc = 5 mhz fc = 4 mhz fc = 2 mhz +100 i ccl - v cc fc = 8 khz i ccl ( m a) 160 140 120 100 80 60 40 20 3.0 4.0 5.0 6.0 v cc (v) t a = +25 c i ccs - v cc fc = 16 mhz i ccs (ma) 10 9 8 7 6 5 4 3 2 1 3.0 4.0 5.0 6.0 v cc (v) t a = +25 c fc = 12.5 mhz fc = 10 mhz fc = 8 mhz fc = 5 mhz fc = 4 mhz fc = 2 mhz i ccs - t a fc = 16 mhz i ccs (ma) 10 9 8 7 6 5 4 3 2 1 C20 +10 +40 +70 t a ( c) v cc = 5.0 v fc = 12.5 mhz fc = 10 mhz fc = 8 mhz fc = 5 mhz fc = 4 mhz fc = 2 mhz +100 i ccls - v cc fc = 8 khz i ccls (ma) 70 60 50 40 30 20 10 3.0 4.0 5.0 6.0 v cc (v) t a = +25 c
107 mb90570 series i cc - fc i cc (ma) v cc = 2.5 v v cc = 3.0 v v cc = 3.5 v v cc = 4.0 v v cc = 4.5 v v cc = 5.0 v v cc = 5.5 v v cc = 6.0 v 35 30 25 20 15 10 5 4.0 6.0 8.0 12.0 16.0 t a = +25 c i ccs - fc i ccs (ma) v cc = 2.5 v v cc = 3.0 v v cc = 3.5 v v cc = 4.0 v v cc = 4.5 v v cc = 5.0 v v cc = 5.5 v v cc = 6.0 v t a = +25 c 10 9 8 7 6 5 4 3 2 1 fc (mhz) 4.0 6.0 8.0 12.0 16.0 fc (mhz) i cct - v cc i cct ( m a) 20 18 16 14 12 10 8 6 4 2 t a = +25 c 3.0 4.0 5.0 6.0 v cc (v) 3.0 4.0 5.0 6.0 v cc (v) fc = 8 khz i cch - v cc i cch ( m a) 10 9 8 7 6 5 4 3 2 1 t a = +25 c i cclh - t a i cclh ( m a) 10 9 8 7 6 5 4 3 2 1 C20 +10 +40 +70 +100 t a ( c) v cc = 6.0 v v cc = 5.5 v v cc = 5.0 v v cc = 4.5 v v cc = 4.0 v v cc = 3.5 v v cc = 3.0 v v cc = 2.5 v v cc = 6.0 v v cc = 5.5 v v cc = 5.0 v v cc = 4.5 v v cc = 4.0 v v cc = 3.5 v v cc = 3.0 v v cc = 2.5 v C20 +10 +40 +70 +100 t a ( c) i cct - t a i cct ( m a) 10 9 8 7 6 5 4 3 2 1
108 mb90570 series (2) power supply current (mb90f574 ) 20 18 16 14 12 10 8 6 4 2 i ccl - t a v cc = 6.0 v v cc = 5.5 v v cc = 5.0 v v cc = 4.5 v v cc = 4.0 v v cc = 3.5 v v cc = 3.0 v v cc = 2.5 v C20 +10 +40 +70 +100 t a ( c) 14 12 10 8 6 4 2 v cc = 6.0 v v cc = 5.5 v v cc = 5.0 v v cc = 4.5 v v cc = 4.0 v v cc = 3.5 v v cc = 3.0 v v cc = 2.5 v i ccl ( m a) i ccls - t a i ccls ( m a) C20 +10 +40 +70 +100 t a ( c) 140 120 100 80 60 40 20 i cc - t a i cc (ma) fc = 16 mhz fc = 12.5 mhz fc = 10 mhz fc = 8 mhz fc = 5 mhz fc = 4 mhz fc = 2 mhz 3.0 4.0 5.0 6.0 t a = +25 c v cc (v) i ccs - v cc i ccs (ma) 40 35 30 25 20 15 10 5 3.0 4.0 5.0 6.0 v cc (v) fc = 16 mhz fc = 12.5 mhz fc = 10 mhz fc = 8 mhz fc = 5 mhz fc = 4 mhz fc = 2 mhz t a = +25 c i cc - v cc i cc (ma) 120 100 80 60 40 20 fc = 16 mhz fc = 12.5 mhz fc = 10 mhz fc = 8 mhz fc = 5 mhz fc = 4 mhz fc = 2 mhz 40 35 30 25 20 15 10 5 fc = 16 mhz fc = 12.5 mhz fc = 10 mhz fc = 8 mhz fc = 5 mhz fc = 4 mhz fc = 2 mhz i ccs - t a i ccs (ma) v cc = 5.0 v v cc = 5.0 v C20 +10 +40 +70 +100 t a ( c) C20 +10 +40 +70 +100 t a ( c)
109 mb90570 series 50 40 30 20 10 3 4 5 6 i cct ( m a) v cc (v) i cct - v cc t a = + 25 c i cch ( m a) i cch -v cc f c = 8 kh z 10 9 8 7 6 5 4 3 2 1 3.0 4.0 5.0 6.0 v cc (v) 120 100 80 60 40 20 4.0 8.0 12.0 i cc (ma) f c (mh z ) i cc - f c v cc = 4.0 v v cc = 3.5 v v cc = 3.0 v v cc = 2.5 v v cc = 4.5 v v cc = 5.0 v v cc = 6.0 v 16.0 v cc = 5.5 v 35 30 20 15 10 5 4.0 8.0 12.0 i ccs (ma) f c (mh z ) i ccs - f c v cc = 4.0 v v cc = 3.5 v v cc = 3.0 v v cc = 2.5 v v cc = 4.5 v v cc = 5.0 v v cc = 6.0 v 16.0 v cc = 5.5 v 25 40 140 120 100 80 60 40 20 3.0 4.0 5.0 6.0 i ccls ( m a) v cc (v) i ccls - v cc t a = + 25 c f c = 8 khz 160 180 200 t a = + 25 c t a = + 25 c t a = + 25 c
110 mb90570 series i cch ( m a) i cch - t a 10 9 5 4 3 2 1 -20 +10 +70 +100 i cct ( m a) t a ( c) i cct - t a 6 7 8 +40 v cc = 4.0 v v cc = 3.5 v v cc = 3.0 v v cc = 2.5 v v cc = 4.5 v v cc = 5.0 v v cc = 6.0 v v cc = 5.5 v 10 9 5 4 3 2 1 -20 +10 +70 +100 t a ( c) 6 7 8 +40 20 18 10 8 6 4 2 -20 +10 +70 +100 i ccls ( m a) t a ( c) 12 14 16 +40 v cc = 4.0 v v cc = 3.5 v v cc = 3.0 v v cc = 2.5 v v cc = 4.5 v v cc = 5.0 v v cc = 6.0 v v cc = 5.5 v i ccls - t a v cc = 4.0 v v cc = 3.5 v v cc = 3.0 v v cc = 2.5 v v cc = 4.5 v v cc = 5.0 v v cc = 6.0 v v cc = 5.5 v
111 mb90570 series (3)power supply current (MB90574C) 50 45 40 35 30 25 20 15 10 5 0 - 50 - 20 10 40 70 100 f c = 16 mhz f c = 12 mhz f c = 10 mhz f c = 8 mhz f c = 5 mhz f c = 4 mhz f c = 2 mhz i cc (ma) v cc = 5.0 v i cc - t a t a ( c) 0 10 20 30 40 50 60 70 246 8 10 14 12 16 v cc = 6.0 v v cc = 5.5 v v cc = 5.0 v v cc = 4.5 v v cc = 4.0 v v cc = 3.5 v v cc = 3.0 v i cc (ma) t a = +25 c i cc - f c f c (mhz) 0 2 4 6 8 10 12 14 16 18 3.000 3.500 4.000 4.500 5.000 5.500 6.000 f c = 16 mhz f c = 12 mhz f c = 10 mhz f c = 8 mhz f c = 5 mhz f c = 4 mhz f c = 2 mhz i ccs (ma) t a = +25 c i ccs - v cc v cc (v) 0 2 6 4 8 12 10 14 16 18 - 50 - 20 10 40 70 100 f c = 16 mhz f c = 12 mhz f c = 10 mhz f c = 8 mhz f c = 4 mhz f c = 2 mhz i ccs (ma) v cc = 5 v i ccs - t a t a ( c) 0 10 20 30 40 50 60 70 3.0 3.5 4.0 4.5 5.0 5.5 6.0 f c = 16 mhz f c = 12 mhz f c = 10 mhz f c = 8 mhz f c = 5 mhz f c = 4 mhz f c = 2 mhz i cc (ma) t a = +25 c i cc - v cc v cc (v) 18 16 14 12 10 8 6 4 2 0 2 4 6 8 10 12 14 16 v cc = 6.0 v v cc = 5.5 v v cc = 5.0 v v cc = 4.5 v v cc = 4.0 v v cc = 3.5 v v cc = 3.0 v i ccs (ma) t a = +25 c i ccs - f c f c (mhz)
112 mb90570 series 10 9 8 7 6 5 4 3 2 1 0 3.000 3.500 4.000 4.500 5.000 5.500 6.000 v cc (v) i cch ( m a) i cch - v cc t a = +25 c 10 9 8 7 6 5 4 3 2 1 0 3.000 3.500 4.000 4.500 5.000 5.500 6.000 v cc (v) i cct ( m a) i cct - v cc t a = +25 c f c = 8 khz 10 9 8 7 6 5 4 3 2 1 0 - 50 - 20 10 40 70 100 t a ( c) i cct ( m a) i cct - t a v cc = 6.0 v v cc = 5.5 v v cc = 5.0 v v cc = 4.5 v v cc = 4.0 v v cc = 3.5 v v cc = 3.0 v 10 9 8 7 6 5 4 3 2 1 0 - 50 - 20 10 40 70 100 t a ( c) i cch ( m a) i cch - t a v cc = 6.0 v v cc = 5.5 v v cc = 5.0 v v cc = 4.5 v v cc = 4.0 v v cc = 3.5 v v cc = 3.0 v 70 60 50 40 30 20 10 0 3.000 3.500 4.000 4.500 5.000 5.500 6.000 v cc (v) i ccl ( m a) i ccl - v cc t a = +25 c f c = 8 khz 70 60 50 40 30 20 10 0 - 50 - 20 10 40 70 100 t a ( c) i ccl ( m a) i ccl - t a v cc = 6.0 v v cc = 5.5 v v cc = 5.0 v v cc = 4.5 v v cc = 4.0 v v cc = 3.5 v v cc = 3.0 v
113 mb90570 series 25 20 15 10 5 0 3.000 3.500 4.000 4.500 5.000 5.500 6.000 v cc (v) i ccls ( m a) i ccls - v cc t a = +25 c f c = 8 khz 25 20 15 10 5 0 - 50 - 20 10 40 70 100 t a ( c) i ccls ( m a) i ccls - t a v cc = 6.0 v v cc = 5.5 v v cc = 5.0 v v cc = 4.5 v v cc = 4.0 v v cc = 3.5 v v cc = 3.0 v
114 mb90570 series n n n n instructions (351 instructions) table 1 explanation of items in tables of instructions ? number of execution cycles the number of cycles required for instruction execution is acquired by adding the number of cycles for each instruction, a corrective value depending on the condition, and the number of cycles required for program fetch. whenever the instruction being executed exceeds the two-byte (word) boundary, a program on an internal rom connected to a 16-bit bus is fetched. if data access is interfered with, therefore, the number of execution cycles is increased. for each byte of the instruction being executed, a program on a memory connected to an 8-bit external data bus is fetched. if data access in interfered with, therefore, the number of execution cycles is increased. when a general-purpose register, an internal rom, an internal ram, an internal i/o device, or an external bus is accessed during intermittent cpu operation, the cpu clock is suspended by the number of cycles specified by the cg1/0 bit of the low-power consumption mode control register. when determining the number of cycles required for instruction execution during intermittent cpu operation, therefore, add the value of the number of times access is done the number of cycles suspended as the corrective value to the number of ordinary execution cycles. item meaning mnemonic upper-case letters and symbols: represented as they appear in assembler. lower-case letters: replaced when described in assembler. numbers after lower-case letters: indicate the bit width within the instruction code. # indicates the number of bytes. ~ indicates the number of cycles. m : when branching n : when not branching see table 4 for details about meanings of other letters in items. rg indicates the number of accesses to the register during execution of the instruction. it is used calculate a correction value for intermittent operation of cpu. b indicates the correction value for calculating the number of actual cycles during execution of the instruction. (table 5) the number of actual cycles during execution of the instruction is the correction value summed with the value in the ~ column. operation indicates the operation of instruction. lh indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator. z : transfers 0. x : extends with a sign before transferring. C : transfers nothing. ah indicates special operations involving the upper 16 bits in the accumulator. * : transfers from al to ah. C : no transfer. z : transfers 00 h to ah. x : transfers 00 h or ff h to ah by signing and extending al. i indicates the status of each of the following flags: i (interrupt enable), s (stack), t (sticky bit), n (negative), z (zero), v (overflow), and c (carry). * : changes due to execution of instruction. C : no change. s : set by execution of instruction. r : reset by execution of instruction. s t n z v c rmw indicates whether the instruction is a read-modify-write instruction. (a single instruction that reads data from memory, etc., processes the data, and then writes the result to memory.) * : instruction is a read-modify-write instruction. C : instruction is not a read-modify-write instruction. note: a read-modify-write instruction cannot be used on addresses that have different meanings depending on whether they are read or written.
115 mb90570 series table 2 explanation of symbols in tables of instructions symbol meaning a 32-bit accumulator the bit length varies according to the instruction. byte : lower 8 bits of al word : 16 bits of al long : 32 bits of al and ah ah al upper 16 bits of a lower 16 bits of a sp stack pointer (usp or ssp) pc program counter pcb program bank register dtb data bank register adb additional data bank register ssb system stack bank register usb user stack bank register spb current stack bank register (ssb or usb) dpr direct page register brg1 dtb, adb, ssb, usb, dpr, pcb, spb brg2 dtb, adb, ssb, usb, dpr, spb ri r0, r1, r2, r3, r4, r5, r6, r7 rwi rw0, rw1, rw2, rw3, rw4, rw5, rw6, rw7 rwj rw0, rw1, rw2, rw3 rli rl0, rl1, rl2, rl3 dir compact direct addressing addr16 addr24 ad24 0 to 15 ad24 16 to 23 direct addressing physical direct addressing bit 0 to bit 15 of addr24 bit 16 to bit 23 of addr24 io i/o area (000000 h to 0000ff h ) imm4 imm8 imm16 imm32 ext (imm8) 4-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 16-bit data signed and extended from 8-bit immediate data disp8 disp16 8-bit displacement 16-bit displacement bp bit offset vct4 vct8 vector number (0 to 15) vector number (0 to 255) ( )b bit address rel pc relative addressing ear eam effective addressing (codes 00 to 07) effective addressing (codes 08 to 1f) rlst register list
116 mb90570 series table 3 effective address fields note : the number of bytes in the address extension is indicated by the + symbol in the # (number of bytes) column in the tables of instructions. code notation address format number of bytes in address extension * 00 01 02 03 04 05 06 07 r0 r1 r2 r3 r4 r5 r6 r7 rw0 rw1 rw2 rw3 rw4 rw5 rw6 rw7 rl0 (rl0) rl1 (rl1) rl2 (rl2) rl3 (rl3) register direct ea corresponds to byte, word, and long-word types, starting from the left 08 09 0a 0b @rw0 @rw1 @rw2 @rw3 register indirect 0 0c 0d 0e 0f @rw0 + @rw1 + @rw2 + @rw3 + register indirect with post-increment 0 10 11 12 13 14 15 16 17 @rw0 + disp8 @rw1 + disp8 @rw2 + disp8 @rw3 + disp8 @rw4 + disp8 @rw5 + disp8 @rw6 + disp8 @rw7 + disp8 register indirect with 8-bit displacement 1 18 19 1a 1b @rw0 + disp16 @rw1 + disp16 @rw2 + disp16 @rw3 + disp16 register indirect with 16-bit displacement 2 1c 1d 1e 1f @rw0 + rw7 @rw1 + rw7 @pc + disp16 addr16 register indirect with index register indirect with index pc indirect with 16-bit displacement direct address 0 0 2 2
117 mb90570 series table 4 number of execution cycles for each type of addressing note : (a) is used in the ~ (number of states) column and column b (correction value) in the tables of instructions. table 5 compensation values for number of cycles used to calculate number of actual cycles notes: (b), (c), and (d) are used in the ~ (number of states) column and column b (correction value) in the tables of instructions. when the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. table 6 correction values for number of cycles used to calculate number of program fetch cycles notes: when the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. because instruction execution is not slowed down by all program fetches in actuality, these correction values should be used for worst case calculations. code operand (a) number of register accesses for each type of addressing number of execution cycles for each type of addressing 00 to 07 ri rwi rli listed in tables of instructions listed in tables of instructions 08 to 0b @rwj 2 1 0c to 0f @rwj + 4 2 10 to 17 @rwi + disp8 2 1 18 to 1b @rwj + disp16 2 1 1c 1d 1e 1f @rw0 + rw7 @rw1 + rw7 @pc + disp16 addr16 4 4 2 1 2 2 0 0 operand (b) byte (c) word (d) long cycles access cycles access cycles access internal register +0 1 +0 1 +0 2 internal memory even address internal memory odd address +0 +0 1 1 +0 +2 1 2 +0 +4 2 4 even address on external data bus (16 bits) odd address on external data bus (16 bits) +1 +1 1 1 +1 +4 1 2 +2 +8 2 4 external data bus (8 bits) +1 1 +4 2 +8 4 instruction byte boundary word boundary internal memory +2 external data bus (16 bits) +3 external data bus (8 bits) +3
118 mb90570 series table 7 transfer instructions (byte) [41 instructions] note : for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah i s t n z v c rmw mov a, dir mov a, addr16 mov a, ri mov a, ear mov a, eam mov a, io mov a, #imm8 mov a, @a mov a, @rli+disp8 movn a, #imm4 movx a, dir movx a, addr16 movx a, ri movx a, ear movx a, eam movx a, io movx a, #imm8 movx a, @a movx a,@rwi+disp8 movx a, @rli+disp8 mov dir, a mov addr16, a mov ri, a mov ear, a mov eam, a mov io, a mov @rli+disp8, a mov ri, ear mov ri, eam mov ear, ri mov eam, ri mov ri, #imm8 mov io, #imm8 mov dir, #imm8 mov ear, #imm8 mov eam, #imm8 mov @al, ah /mov @a, t xch a, ear xch a, eam xch ri, ear xch ri, eam 2 3 1 2 2+ 2 2 2 3 1 2 3 2 2 2+ 2 2 2 2 3 2 3 1 2 2+ 2 3 2 2+ 2 2+ 2 3 3 3 3+ 2 2 2+ 2 2+ 3 4 2 2 3+ (a) 3 2 3 10 1 3 4 2 2 3+ (a) 3 2 3 5 10 3 4 2 2 3+ (a) 3 10 3 4+ (a) 4 5+ (a) 2 5 5 2 4+ (a) 3 4 5+ (a) 7 9+ (a) 0 0 1 1 0 0 0 0 2 0 0 0 1 1 0 0 0 0 1 2 0 0 1 1 0 0 2 2 1 2 1 1 0 0 1 0 0 2 0 4 2 (b) (b) 0 0 (b) (b) 0 (b) (b) 0 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) 0 0 (b) (b) (b) 0 (b) 0 (b) 0 (b) (b) 0 (b) (b) 0 2 (b) 0 2 (b) byte (a) ? (dir) byte (a) ? (addr16) byte (a) ? (ri) byte (a) ? (ear) byte (a) ? (eam) byte (a) ? (io) byte (a) ? imm8 byte (a) ? ((a)) byte (a) ? ((rli)+disp8) byte (a) ? imm4 byte (a) ? (dir) byte (a) ? (addr16) byte (a) ? (ri) byte (a) ? (ear) byte (a) ? (eam) byte (a) ? (io) byte (a) ? imm8 byte (a) ? ((a)) byte (a) ? ((rwi)+disp8) byte (a) ? ((rli)+disp8) byte (dir) ? (a) byte (addr16) ? (a) byte (ri) ? (a) byte (ear) ? (a) byte (eam) ? (a) byte (io) ? (a) byte ((rli) +disp8) ? (a) byte (ri) ? (ear) byte (ri) ? (eam) byte (ear) ? (ri) byte (eam) ? (ri) byte (ri) ? imm8 byte (io) ? imm8 byte (dir) ? imm8 byte (ear) ? imm8 byte (eam) ? imm8 byte ((a)) ? (ah) byte (a) ? (ear) byte (a) ? (eam) byte (ri) ? (ear) byte (ri) ? (eam) z z z z z z z z z z x x x x x x x x x x C C C C C C C C C C C C C C C C C z z C C * * * * * * * C * * * * * * * * * C * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * r * * * * * * * * * * * * * * * * * * * * * * C C * C * C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C C * C * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
119 mb90570 series table 8 transfer instructions (word/long word) [38 instructions] note : for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg boperation lh ah i s t n z v c rmw movw a, dir movw a, addr16 movw a, sp movw a, rwi movw a, ear movw a, eam movw a, io movw a, @a movw a, #imm16 movw a, @rwi+disp8 movw a, @rli+disp8 movw dir, a movw addr16, a movw sp, a movw rwi, a movw ear, a movw eam, a movw io, a movw @rwi+disp8, a movw @rli+disp8, a movw rwi, ear movw rwi, eam movw ear, rwi movw eam, rwi movw rwi, #imm16 movw io, #imm16 movw ear, #imm16 movw eam, #imm16 movw @al, ah /movw@a, t xchw a, ear xchw a, eam xchw rwi, ear xchw rwi, eam 2 3 1 1 2 2+ 2 2 3 2 3 2 3 1 1 2 2+ 2 2 3 2 2+ 2 2+ 3 4 4 4+ 2 2 2+ 2 2+ 3 4 1 2 2 3+ (a) 3 3 2 5 10 3 4 1 2 2 3+ (a) 3 5 10 3 4+ (a) 4 5+ (a) 2 5 2 4+ (a) 3 4 5+ (a) 7 9+ (a) 0 0 0 1 1 0 0 0 0 1 2 0 0 0 1 1 0 0 1 2 2 1 2 1 1 0 1 0 0 2 0 4 2 (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) (c) (c) 0 0 0 (c) (c) (c) (c) (0) (c) 0 (c) 0 (c) 0 (c) (c) 0 2 (c) 0 2 (c) word (a) ? (dir) word (a) ? (addr16) word (a) ? (sp) word (a) ? (rwi) word (a) ? (ear) word (a) ? (eam) word (a) ? (io) word (a) ? ((a)) word (a) ? imm16 word (a) ? ((rwi) +disp8) word (a) ? ((rli) +disp8) word (dir) ? (a) word (addr16) ? (a) word (sp) ? (a) word (rwi) ? (a) word (ear) ? (a) word (eam) ? (a) word (io) ? (a) word ((rwi) +disp8) ? (a) word ((rli) +disp8) ? (a) word (rwi) ? (ear) word (rwi) ? (eam) word (ear) ? (rwi) word (eam) ? (rwi) word (rwi) ? imm16 word (io) ? imm16 word (ear) ? imm16 word (eam) ? imm16 word ((a)) ? (ah) word (a) ? (ear) word (a) ? (eam) word (rwi) ? (ear) word (rwi) ? (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * C * C * C C C C * * * * * * * * * * * * * * * * * * * * * * * * * C * C * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C movl a, ear movl a, eam movl a, #imm32 movl ear, a movl eam, a 2 2+ 5 2 2+ 4 5+ (a) 3 4 5+ (a) 2 0 0 2 0 0 (d) 0 0 (d) long (a) ? (ear) long (a) ? (eam) long (a) ? imm32 long (ear) ? (a) long (eam) ? (a) C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * C C C C C C C C C C C C C C C
120 mb90570 series table 9 addition and subtraction instructions (byte/word/long word) [42 instructions] note : for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg boperation lh ah i s t n z v c rmw add a,#imm8 add a, dir add a, ear add a, eam add ear, a add eam, a addc a addc a, ear addc a, eam adddc a sub a, #imm8 sub a, dir sub a, ear sub a, eam sub ear, a sub eam, a subc a subc a, ear subc a, eam subdc a 2 2 2 2+ 2 2+ 1 2 2+ 1 2 2 2 2+ 2 2+ 1 2 2+ 1 2 5 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 2 5 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 0 0 1 0 2 0 0 1 0 0 0 0 1 0 2 0 0 1 0 0 0 (b) 0 (b) 0 2 (b) 0 0 (b) 0 0 (b) 0 (b) 0 2 (b) 0 0 (b) 0 byte (a) ? (a) +imm8 byte (a) ? (a) +(dir) byte (a) ? (a) +(ear) byte (a) ? (a) +(eam) byte (ear) ? (ear) + (a) byte (eam) ? (eam) + (a) byte (a) ? (ah) + (al) + (c) byte (a) ? (a) + (ear) + (c) byte (a) ? (a) + (eam) + (c) byte (a) ? (ah) + (al) + (c) (decimal) byte (a) ? (a) Cimm8 byte (a) ? (a) C (dir) byte (a) ? (a) C (ear) byte (a) ? (a) C (eam) byte (ear) ? (ear) C (a) byte (eam) ? (eam) C (a) byte (a) ? (ah) C (al) C (c) byte (a) ? (a) C (ear) C (c) byte (a) ? (a) C (eam) C (c) byte (a) ? (ah) C (al) C (c) (decimal) z z z z C z z z z z z z z z C C z z z z C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C C C C C * C C C C C C C C C * C C C C addw a addw a, ear addw a, eam addw a, #imm16 addw ear, a addw eam, a addcw a, ear addcw a, eam subw a subw a, ear subw a, eam subw a, #imm16 subw ear, a subw eam, a subcw a, ear subcw a, eam 1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+ 2 3 4+ (a) 2 3 5+ (a) 3 4+ (a) 2 3 4+ (a) 2 3 5+ (a) 3 4+ (a) 0 1 0 0 2 0 1 0 0 1 0 0 2 0 1 0 0 0 (c) 0 0 2 (c) 0 (c) 0 0 (c) 0 0 2 (c) 0 (c) word (a) ? (ah) + (al) word (a) ? (a) +(ear) word (a) ? (a) +(eam) word (a) ? (a) +imm16 word (ear) ? (ear) + (a) word (eam) ? (eam) + (a) word (a) ? (a) + (ear) + (c) word (a) ? (a) + (eam) + (c) word (a) ? (ah) C (al) word (a) ? (a) C (ear) word (a) ? (a) C (eam) word (a) ? (a) Cimm16 word (ear) ? (ear) C (a) word (eam) ? (eam) C (a) word (a) ? (a) C (ear) C (c) word (a) ? (a) C (eam) C (c) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C C C C C * C C C C C C C * C C addl a, ear addl a, eam addl a, #imm32 subl a, ear subl a, eam subl a, #imm32 2 2+ 5 2 2+ 5 6 7+ (a) 4 6 7+ (a) 4 2 0 0 2 0 0 0 (d) 0 0 (d) 0 long (a) ? (a) + (ear) long (a) ? (a) + (eam) long (a) ? (a) +imm32 long (a) ? (a) C (ear) long (a) ? (a) C (eam) long (a) ? (a) Cimm32 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * C C C C C C
121 mb90570 series table 10 increment and decrement instructions (byte/word/long word) [12 instructions] note : for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. table 11 compare instructions (byte/word/long word) [11 instructions] note : for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah i s t n z v c rmw inc ear inc eam dec ear dec eam 2 2+ 2 2+ 2 5+ (a) 3 5+ (a) 2 0 2 0 0 2 (b) 0 2 (b) byte (ear) ? (ear) +1 byte (eam) ? (eam) +1 byte (ear) ? (ear) C1 byte (eam) ? (eam) C1 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C C C * C * incw ear incw eam decw ear decw eam 2 2+ 2 2+ 3 5+ (a) 3 5+ (a) 2 0 2 0 0 2 (c) 0 2 (c) word (ear) ? (ear) +1 word (eam) ? (eam) +1 word (ear) ? (ear) C1 word (eam) ? (eam) C1 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C C C * C * incl ear incl eam decl ear decl eam 2 2+ 2 2+ 7 9+ (a) 7 9+ (a) 4 0 4 0 0 2 (d) 0 2 (d) long (ear) ? (ear) +1 long (eam) ? (eam) +1 long (ear) ? (ear) C1 long (eam) ? (eam) C1 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C C C * C * mnemonic # ~ rg b operation lh ah i s t n z v c rmw cmp a cmp a, ear cmp a, eam cmp a, #imm8 1 2 2+ 2 1 2 3+ (a) 2 0 1 0 0 0 0 (b) 0 byte (ah) C (al) byte (a) ? (ear) byte (a) ? (eam) byte (a) ? imm8 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * C C C C cmpw a cmpw a, ear cmpw a, eam cmpw a, #imm16 1 2 2+ 3 1 2 3+ (a) 2 0 1 0 0 0 0 (c) 0 word (ah) C (al) word (a) ? (ear) word (a) ? (eam) word (a) ? imm16 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * C C C C cmpl a, ear cmpl a, eam cmpl a, #imm32 2 2+ 5 6 7+ (a) 3 2 0 0 0 (d) 0 word (a) ? (ear) word (a) ? (eam) word (a) ? imm32 C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C
122 mb90570 series table 12 multiplication and division instructions (byte/word/long word) [11 instructions] *1: 3 when the result is zero, 7 when an overflow occurs, and 15 normally. *2: 4 when the result is zero, 8 when an overflow occurs, and 16 normally. *3: 6 + (a) when the result is zero, 9 + (a) when an overflow occurs, and 19 + (a) normally. *4: 4 when the result is zero, 7 when an overflow occurs, and 22 normally. *5: 6 + (a) when the result is zero, 8 + (a) when an overflow occurs, and 26 + (a) normally. *6: (b) when the result is zero or when an overflow occurs, and 2 (b) normally. *7: (c) when the result is zero or when an overflow occurs, and 2 (c) normally. *8: 3 when byte (ah) is zero, and 7 when byte (ah) is not zero. *9: 4 when byte (ear) is zero, and 8 when byte (ear) is not zero. *10: 5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0. *11: 3 when word (ah) is zero, and 11 when word (ah) is not zero. *12: 4 when word (ear) is zero, and 12 when word (ear) is not zero. *13: 5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not zero. note : for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah i s t n z v c rmw divu a divu a, ear divu a, eam divuw a, ear divuw a, eam mulu a mulu a, ear mulu a, eam muluw a muluw a, ear muluw a, eam 1 2 2+ 2 2+ 1 2 2+ 1 2 2+ * 1 * 2 * 3 * 4 * 5 * 8 * 9 * 10 * 11 * 12 * 13 0 1 0 1 0 0 1 0 0 1 0 0 0 * 6 0 * 7 0 0 (b) 0 0 (c) word (ah) /byte (al) quotient ? byte (al) remainder ? byte (ah) word (a)/byte (ear) quotient ? byte (a) remainder ? byte (ear) word (a)/byte (eam) quotient ? byte (a) remainder ? byte (eam) long (a)/word (ear) quotient ? word (a) remainder ? word (ear) long (a)/word (eam) quotient ? word (a) remainder ? word (eam) byte (ah) *byte (al) ? word (a) byte (a) *byte (ear) ? word (a) byte (a) *byte (eam) ? word (a) word (ah) *word (al) ? long (a) word (a) *word (ear) ? long (a) word (a) *word (eam) ? long (a) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * C C C C C C * * * * * C C C C C C C C C C C C C C C C C
123 mb90570 series table 13 signed multiplication and division instructions (byte/word/long word) [11 instructions] *1: set to 3 when the division-by-0, 8 or 18 for an overflow, and 18 for normal operation. *2: set to 3 when the division-by-0, 10 or 21 for an overflow, and 22 for normal operation. *3: set to 4 + (a) when the division-by-0, 11 + (a) or 22 + (a) for an overflow, and 23 + (a) for normal operation. *4: positive dividend: set to 4 when the division-by-0, 10 or 29 for an overflow, and 30 for normal operation. negative dividend: set to 4 when the division-by-0, 11 or 30 for an overflow and 31 for normal operation. *5: positive dividend: set to 4 + (a) when the division-by-0, 11 + (a) or 30 + (a) for an overflow, and 31 + (a) for normal operation. negative dividend: set to 4 + (a) when the division-by-0, 12 + (a) or 31 + (a) for an overflow, and 32 + (a) for normal operation. *6: when the division-by-0, (b) for an overflow, and 2 (b) for normal operation. *7: when the division-by-0, (c) for an overflow, and 2 (c) for normal operation. *8: set to 3 when byte (ah) is zero, 12 when the result is positive, and 13 when the result is negative. *9: set to 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative. *10: set to 4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive, and 14 + (a) when the result is negative. *11: set to 3 when word (ah) is zero, 12 when the result is positive, and 13 when the result is negative. *12: set to 3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative. *13: set to 4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is negative. notes: ? when overflow occurs during div or divw instruction execution, the number of execution cycles takes two values because of detection before and after an operation. ? when overflow occurs during div or divw instruction execution, the contents of al are destroyed. ? for (a) to (d), refer to table 4 number of execution cycles for effective address in addressing modes and table 5 correction values for number of cycles for calculating actual number of cycles. mnemonic # ~ rg boperation lh ah i s t n z v c rmw div a div a, ear div a, eam divw a, ear divw a, eam mulu a mulu a, ear mulu a, eam muluw a muluw a, ear muluw a, eam 2 2 2 + 2 2+ 2 2 2 + 2 2 2 + *1 *2 *3 *4 *5 *8 *9 *10 *11 *12 *13 0 1 0 1 0 0 1 0 0 1 0 0 0 *6 0 *7 0 0 (b) 0 0 (c) word (ah) /byte (al) quotient ? byte (al) remainder ? byte (ah) word (a)/byte (ear) quotient ? byte (a) remainder ? byte (ear) word (a)/byte (eam) quotient ? byte (a) remainder ? byte (eam) long (a)/word (ear) quotient ? word (a) remainder ? word (ear) long (a)/word (eam) quotient ? word (a) remainder ? word (eam) byte (ah) *byte (al) ? word (a) byte (a) *byte (ear) ? word (a) byte (a) *byte (eam) ? word (a) word (ah) *word (al) ? long (a) word (a) *word (ear) ? long (a) word (a) *word (eam) ? long (a) z z z C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * C C C C C C * * * * * C C C C C C C C C C C C C C C C C
124 mb90570 series table 14 logical 1 instructions (byte/word) [39 instructions ] note : for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah i s t n z v c rmw and a, #imm8 and a, ear and a, eam and ear, a and eam, a or a, #imm8 or a, ear or a, eam or ear, a or eam, a xor a, #imm8 xor a, ear xor a, eam xor ear, a xor eam, a not a not ear not eam 2 2 2+ 2 2+ 2 2 2+ 2 2+ 2 2 2+ 2 2+ 1 2 2+ 2 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 5+ (a) 2 3 5+ (a) 0 1 0 2 0 0 1 0 2 0 0 1 0 2 0 0 2 0 0 0 (b) 0 2 (b) 0 0 (b) 0 2 (b) 0 0 (b) 0 2 (b) 0 0 2 (b) byte (a) ? (a) and imm8 byte (a) ? (a) and (ear) byte (a) ? (a) and (eam) byte (ear) ? (ear) and (a) byte (eam) ? (eam) and (a) byte (a) ? (a) or imm8 byte (a) ? (a) or (ear) byte (a) ? (a) or (eam) byte (ear) ? (ear) or (a) byte (eam) ? (eam) or (a) byte (a) ? (a) xor imm8 byte (a) ? (a) xor (ear) byte (a) ? (a) xor (eam) byte (ear) ? (ear) xor (a) byte (eam) ? (eam) xor (a) byte (a) ? not (a) byte (ear) ? not (ear) byte (eam) ? not (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * r r r r r r r r r r r r r r r r r r C C C C C C C C C C C C C C C C C C C C C C * C C C C * C C C C * C C * andw a andw a, #imm16 andw a, ear andw a, eam andw ear, a andw eam, a orw a orw a, #imm16 orw a, ear orw a, eam orw ear, a orw eam, a xorw a xorw a, #imm16 xorw a, ear xorw a, eam xorw ear, a xorw eam, a notw a notw ear notw eam 1 3 2 2+ 2 2+ 1 3 2 2+ 2 2+ 1 3 2 2+ 2 2+ 1 2 2+ 2 2 3 4+ (a) 3 5+ (a) 2 2 3 4+ (a) 3 5+ (a) 2 2 3 4+ (a) 3 5+ (a) 2 3 5+ (a) 0 0 1 0 2 0 0 0 1 0 2 0 0 0 1 0 2 0 0 2 0 0 0 0 (c) 0 2 (c) 0 0 0 (c) 0 2 (c) 0 0 0 (c) 0 2 (c) 0 0 2 (c) word (a) ? (ah) and (a) word (a) ? (a) and imm16 word (a) ? (a) and (ear) word (a) ? (a) and (eam) word (ear) ? (ear) and (a) word (eam) ? (eam) and (a) word (a) ? (ah) or (a) word (a) ? (a) or imm16 word (a) ? (a) or (ear) word (a) ? (a) or (eam) word (ear) ? (ear) or (a) word (eam) ? (eam) or (a) word (a) ? (ah) xor (a) word (a) ? (a) xor imm16 word (a) ? (a) xor (ear) word (a) ? (a) xor (eam) word (ear) ? (ear) xor (a) word (eam) ? (eam) xor (a) word (a) ? not (a) word (ear) ? not (ear) word (eam) ? not (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * r r r r r r r r r r r r r r r r r r r r r C C C C C C C C C C C C C C C C C C C C C C C C C C * C C C C C * C C C C C * C C *
125 mb90570 series table 15 logical 2 instructions (long word) [6 instructions] note : for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. table 16 sign inversion instructions (byte/word) [6 instructions] note : for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. table 17 normalize instruction (long word) [1 instruction] *1: 4 when the contents of the accumulator are all zeroes, 6 + (r0) in all other cases (shift count). note : for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg boperation lh ah i s t n z v c rmw andl a, ear andl a, eam orl a, ear orl a, eam xorl a, ea xorl a, eam 2 2+ 2 2+ 2 2+ 6 7+ (a) 6 7+ (a) 6 7+ (a) 2 0 2 0 2 0 0 (d) 0 (d) 0 (d) long (a) ? (a) and (ear) long (a) ? (a) and (eam) long (a) ? (a) or (ear) long (a) ? (a) or (eam) long (a) ? (a) xor (ear) long (a) ? (a) xor (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * r r r r r r C C C C C C C C C C C C mnemonic # ~ rg b operation lh ah i s t n z v c rmw neg a neg ear neg eam 1 2 2+ 2 3 5+ (a) 0 2 0 0 0 2 (b) byte (a) ? 0 C (a) byte (ear) ? 0 C (ear) byte (eam) ? 0 C (eam) x C C C C C C C C C C C C C C * * * * * * * * * * * * C C * negw a negw ear negw eam 1 2 2+ 2 3 5+ (a) 0 2 0 0 0 2 (c) word (a) ? 0 C (a) word (ear) ? 0 C (ear) word (eam) ? 0 C (eam) C C C C C C C C C C C C C C C * * * * * * * * * * * * C C * mnemonic # ~ rg b operation lh ah i s t n z v c rmw nrml a, r0 2 * 1 1 0 long (a) ? shift until first digit is 1 byte (r0) ? current shift count CCCCCC*CC C
126 mb90570 series table 18 shift instructions (byte/word/long word) [18 instructions] *1: 6 when r0 is 0, 5 + (r0) in all other cases. *2: 6 when r0 is 0, 6 + (r0) in all other cases. note : for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg boperation lh ah i s t n z v c rmw rorc a rolc a rorc ear rorc eam rolc ear rolc eam asr a, r0 lsr a, r0 lsl a, r0 2 2 2 2+ 2 2+ 2 2 2 2 2 3 5+ (a) 3 5+ (a) * 1 * 1 * 1 0 0 2 0 2 0 1 1 1 0 0 0 2 (b) 0 2 (b) 0 0 0 byte (a) ? right rotation with carry byte (a) ? left rotation with carry byte (ear) ? right rotation with carry byte (eam) ? right rotation with carry byte (ear) ? left rotation with carry byte (eam) ? left rotation with carry byte (a) ? arithmetic right barrel shift (a, r0) byte (a) ? logical right barrel shift (a, r0) byte (a) ? logical left barrel shift (a, r0) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * C * * * * * * * * * * * * * * * * * * C C C C C C C C C * * * * * * * * * C C C * C * C C C asrw a lsrw a/shrw a lslw a/shlw a asrw a, r0 lsrw a, r0 lslw a, r0 1 1 1 2 2 2 2 2 2 * 1 * 1 * 1 0 0 0 1 1 1 0 0 0 0 0 0 word (a) ? arithmetic right shift (a, 1 bit) word (a) ? logical right shift (a, 1 bit) word (a) ? logical left shift (a, 1 bit) word (a) ? arithmetic right barrel shift (a, r0) word (a) ? logical right barrel shift (a, r0) word (a) ? logical left barrel shift (a, r0) C C C C C C C C C C C C C C C C C C C C C C C C * * C * * C * r * * * * * * * * * * C C C C C C * * * * * * C C C C C C asrl a, r0 lsrl a, r0 lsll a, r0 2 2 2 * 2 * 2 * 2 1 1 1 0 0 0 long (a) ? arithmetic right shift (a, r0) long (a) ? logical right barrel shift (a, r0) long (a) ? logical left barrel shift (a, r0) C C C C C C C C C C C C * * C * * * * * * C C C * * * C C C
127 mb90570 series table 19 branch 1 instructions [31 instructions] *1: 4 when branching, 3 when not branching. *2: (b) + 3 (c) *3: read (word) branch address. *4: w: save (word) to stack; r: read (word) branch address. *5: save (word) to stack. *6: w: save (long word) to w stack; r: read (long word) r branch address. *7: save (long word) to stack. note : for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg boperation lh ah i s t n z v c rmw bz/beq rel bnz/bne rel bc/blo rel bnc/bhs rel bn rel bp rel bv rel bnv rel bt rel bnt rel blt rel bge rel ble rel bgt rel bls rel bhi rel bra rel jmp @a jmp addr16 jmp @ear jmp @eam jmpp @ear * 3 jmpp @eam * 3 jmpp addr24 call @ear * 4 call @eam * 4 call addr16 * 5 callv #vct4 * 5 callp @ear * 6 callp @eam * 6 callp addr24 * 7 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 3 2 2+ 2 2+ 4 2 2+ 3 1 2 2+ 4 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 2 3 3 4+ (a) 5 6+ (a) 4 6 7+ (a) 6 7 10 11+ (a) 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 0 1 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) 0 (d) 0 (c) 2 (c) (c) 2 (c) 2 (c) * 2 2 (c) branch when (z) = 1 branch when (z) = 0 branch when (c) = 1 branch when (c) = 0 branch when (n) = 1 branch when (n) = 0 branch when (v) = 1 branch when (v) = 0 branch when (t) = 1 branch when (t) = 0 branch when (v) xor (n) = 1 branch when (v) xor (n) = 0 branch when ((v) xor (n)) or (z) = 1 branch when ((v) xor (n)) or (z) = 0 branch when (c) or (z) = 1 branch when (c) or (z) = 0 branch unconditionally word (pc) ? (a) word (pc) ? addr16 word (pc) ? (ear) word (pc) ? (eam) word (pc) ? (ear), (pcb) ? (ear +2) word (pc) ? (eam), (pcb) ? (eam +2) word (pc) ? ad24 0 to 15, (pcb) ? ad24 16 to 23 word (pc) ? (ear) word (pc) ? (eam) word (pc) ? addr16 vector call instruction word (pc) ? (ear) 0 to 15, (pcb) ? (ear) 16 to 23 word (pc) ? (eam) 0 to 15, (pcb) ? (eam) 16 to 23 word (pc) ? addr0 to 15, (pcb) ? addr16 to 23 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
128 mb90570 series table 20 branch 2 instructions [19 instructions] *1: 5 when branching, 4 when not branching *2: 13 when branching, 12 when not branching *3: 7 + (a) when branching, 6 + (a) when not branching *4: 8 when branching, 7 when not branching *5: 7 when branching, 6 when not branching *6: 8 + (a) when branching, 7 + (a) when not branching *7: set to 3 (b) + 2 (c) when an interrupt request occurs, and 6 (c) for return. *8: retrieve (word) from stack *9: retrieve (long word) from stack *10: in the cbne/cwbne instruction, do not use the rwj+ addressing mode. note : for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg boperation lh ah i s t n z v c rmw cbne a, #imm8, rel cwbne a, #imm16, rel cbne ear, #imm8, rel cbne eam, #imm8, rel* 10 cwbne ear, #imm16, rel cwbne eam, #imm16, rel* 10 dbnz ear, rel dbnz eam, rel dwbnz ear, rel dwbnz eam, rel int #vct8 int addr16 intp addr24 int9 reti link #imm8 unlink ret * 8 retp * 9 3 4 4 4+ 5 5+ 3 3+ 3 3+ 2 3 4 1 1 2 1 1 1 * 1 * 1 * 2 * 3 * 4 * 3 * 5 * 6 * 5 * 6 20 16 17 20 15 6 5 4 6 0 0 1 0 1 0 2 2 2 2 0 0 0 0 0 0 0 0 0 0 0 0 (b) 0 (c) 0 2 (b) 0 2 (c) 8 (c) 6 (c) 6 (c) 8 (c) * 7 (c) (c) (c) (d) branch when byte (a) 1 imm8 branch when word (a) 1 imm16 branch when byte (ear) 1 imm8 branch when byte (eam) 1 imm8 branch when word (ear) 1 imm16 branch when word (eam) 1 imm16 branch when byte (ear) = (ear) C 1, and (ear) 1 0 branch when byte (eam) = (eam) C 1, and (eam) 1 0 branch when word (ear) = (ear) C 1, and (ear) 1 0 branch when word (eam) = (eam) C 1, and (eam) 1 0 software interrupt software interrupt software interrupt software interrupt return from interrupt at constant entry, save old frame pointer to stack, set new frame pointer, and allocate local pointer area at constant entry, retrieve old frame pointer from stack. return from subroutine return from subroutine C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C r r r r * C C C C C C C C C C C C C C s s s s * C C C C C C C C C C C C C C C C C C * C C C C * * * * * * * * * * C C C C * C C C C * * * * * * * * * * C C C C * C C C C * * * * * * * * * * C C C C * C C C C * * * * * * C C C C C C C C * C C C C C C C C C C C * C * C C C C C C C C C
129 mb90570 series table 21 other control instructions (byte/word/long word) [28 instructions] *1: pcb, adb, ssb, usb, and spb : 1 state dtb, dpr : 2 states *2: 7 + 3 (pop count) + 2 (last register number to be popped), 7 when rlst = 0 (no transfer register) *3: 29 +3 (push count) C 3 (last register number to be pushed), 8 when rlst = 0 (no transfer register) *4: pop count (c), or push count (c) *5: pop count or push count. note : for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah i s t n z v c rmw pushw a pushw ah pushw ps pushw rlst popw a popw ah popw ps popw rlst jctx @a and ccr, #imm8 or ccr, #imm8 mov rp, #imm8 mov ilm, #imm8 movea rwi, ear movea rwi, eam movea a, ear movea a, eam addsp #imm8 addsp #imm16 mov a, brgl mov brg2, a nop adb dtb pcb spb ncc cmr 1 1 1 2 1 1 1 2 1 2 2 2 2 2 2+ 2 2+ 2 3 2 2 1 1 1 1 1 1 1 4 4 4 * 3 3 3 4 * 2 14 3 3 2 2 3 2+ (a) 1 1+ (a) 3 3 * 1 1 1 1 1 1 1 1 1 0 0 0 * 5 0 0 0 * 5 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) (c) (c) * 4 (c) (c) (c) * 4 6 (c) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 word (sp) ? (sp) C2, ((sp)) ? (a) word (sp) ? (sp) C2, ((sp)) ? (ah) word (sp) ? (sp) C2, ((sp)) ? (ps) (sp) ? (sp) C2n, ((sp)) ? (rlst) word (a) ? ((sp)), (sp) ? ( sp) +2 word (ah) ? ((sp)), (sp) ? ( sp) +2 word (ps) ? ((sp)), (sp) ? ( sp) +2 (rlst) ? ((sp)), (sp) ? (sp) +2n context switch instruction byte (ccr) ? (ccr) and imm8 byte (ccr) ? (ccr) or imm8 byte (rp) ? imm8 byte (ilm) ? imm8 word (rwi) ? ear word (rwi) ? eam word(a) ? ear word (a) ? eam word (sp) ? (sp) +ext (imm8) word (sp) ? (sp) +imm16 byte (a) ? (brgl) byte (brg2) ? (a) no operation prefix code for accessing ad space prefix code for accessing dt space prefix code for accessing pc space prefix code for accessing sp space prefix code for no flag change prefix code for common register bank C C C C C C C C C C C C C C C C C C C z C C C C C C C C C C C C * C C C C C C C C C C * * C C * C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C * * C C C C C C C C C C C C C * C * * * C C C C C C C C * * C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
130 mb90570 series table 22 bit manipulation instructions [21 instructions] *1: 8 when branching, 7 when not branching *2: 7 when branching, 6 when not branching *3: 10 when condition is satisfied, 9 when not satisfied *4: undefined count *5: until condition is satisfied note : for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. table 23 accumulator manipulation instructions (byte/word) [6 instructions] note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah i s t n z v c rmw movb a, dir:bp movb a, addr16:bp movb a, io:bp movb dir:bp, a movb addr16:bp, a movb io:bp, a setb dir:bp setb addr16:bp setb io:bp clrb dir:bp clrb addr16:bp clrb io:bp bbc dir:bp, rel bbc addr16:bp, rel bbc io:bp, rel bbs dir:bp, rel bbs addr16:bp, rel bbs io:bp, rel sbbs addr16:bp, rel wbts io:bp wbtc io:bp 3 4 3 3 4 3 3 4 3 3 4 3 4 5 4 4 5 4 5 3 3 5 5 4 7 7 6 7 7 7 7 7 7 * 1 * 1 * 2 * 1 * 1 * 2 * 3 * 4 * 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (b) (b) (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) (b) (b) (b) (b) (b) (b) 2 (b) * 5 * 5 byte (a) ? (dir:bp) b byte (a) ? (addr16:bp) b byte (a) ? (io:bp) b bit (dir:bp) b ? (a) bit (addr16:bp) b ? (a) bit (io:bp) b ? (a) bit (dir:bp) b ? 1 bit (addr16:bp) b ? 1 bit (io:bp) b ? 1 bit (dir:bp) b ? 0 bit (addr16:bp) b ? 0 bit (io:bp) b ? 0 branch when (dir:bp) b = 0 branch when (addr16:bp) b = 0 branch when (io:bp) b = 0 branch when (dir:bp) b = 1 branch when (addr16:bp) b = 1 branch when (io:bp) b = 1 branch when (addr16:bp) b = 1, bit = 1 wait until (io:bp) b = 1 wait until (io:bp) b = 0 z z z C C C C C C C C C C C C C C C C C C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * C C C C C C C C C C C C C C C * * * * * * C C C C C C * * * * * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * C C C C C C * C C mnemonic # ~ rg boperation lh ah i s t n z v c rmw swap swapw/xchw a,t ext extw zext zextw 1 1 1 1 1 1 3 2 1 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 byte (a) 0 to 7 ? (a) 8 to 15 word (ah) ? (al) byte sign extension word sign extension byte zero extension word zero extension C C x C z C C * C x C z C C C C C C C C C C C C C C C C C C C C * * r r C C * * * * C C C C C C C C C C C C C C C C C C
131 mb90570 series table 24 string instructions [10 instructions] m: rw0 value (counter value) n: loop count *1: 5 when rw0 is 0, 4 + 7 (rw0) for count out, and 7 n + 5 when match occurs *2: 5 when rw0 is 0, 4 + 8 (rw0) in any other case *3: (b) (rw0) + (b) (rw0) when accessing different areas for the source and destination, calculate (b) sepa- rately for each. *4: (b) n *5: 2 (rw0) *6: (c) (rw0) + (c) (rw0) when accessing different areas for the source and destination, calculate (c) separately for each. *7: (c) n *8: 2 (rw0) note : for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg boperation lh ah i s t n z v c rmw movs/movsi movsd sceq/sceqi sceqd fisl/filsi 2 2 2 2 2 * 2 * 2 * 1 * 1 6m +6 * 5 * 5 * 5 * 5 * 5 * 3 * 3 * 4 * 4 * 3 byte transfer @ah+ ? @al+, counter = rw0 byte transfer @ahC ? @alC, counter = rw0 byte retrieval (@ah+) C al, counter = rw0 byte retrieval (@ahC) C al, counter = rw0 byte filling @ah+ ? al, counter = rw0 C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * C C * * * C C * * C C C * * C C C C C C movsw/movswi movswd scweq/scweqi scweqd filsw/filswi 2 2 2 2 2 * 2 * 2 * 1 * 1 6m +6 * 8 * 8 * 8 * 8 * 8 * 6 * 6 * 7 * 7 * 6 word transfer @ah+ ? @al+, counter = rw0 word transfer @ahC ? @alC, counter = rw0 word retrieval (@ah+) C al, counter = rw0 word retrieval (@ahC) C al, counter = rw0 word filling @ah+ ? al, counter = rw0 C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * C C * * * C C * * C C C * * C C C C C C
132 mb90570 series n ordering information part number package remarks mb90573pff mb90574pff mb90f574pff mb90f574apff 120-pin plastic lqfp (fpt-120p-m05) mb90573pfv mb90574pfv MB90574Cpfv mb90f574pfv mb90f574apfv 120-pin plastic qfp (fpt-120p-m13) MB90574Cpmt mb90f574apmt 120-pin plastic lqfp (fpt-120p-m21)
133 mb90570 series n package dimensions c 2000 fujitsu limited f120013s-2c-4 details of "a" part details of "b" part 0.50?.20(.020?008) 0 10 0.40(.016)max 0.15(.006)max 0.15(.006) 0.15(.006) 22.60?.20(.890?008)sq 20.00?.10(.787?004)sq 0.50(.0197) 0.20?.10 (.008?004) 0.08(.003) m 0.125?.05 (.005?002) 0.05(.002)min (stand off) 21.60 14.50 (.850) nom (.571) ref "a" "b" 30 31 60 61 90 91 120 1 lead no. index 3.85(.152)max (mounting height) 0.10(.004) c 1998 fujitsu limited f120006s-3c-4 0.07(.003) m index 16.00?.20(.630?008)sq 14.00?.10(.551?004)sq 130 31 60 91 120 61 90 lead no. (stand off) 0.10?.10 (.004?004) 0.25(.010) (.018/.030) 0.45/0.75 (.020?008) 0.50?.20 (mounting height) 0~8 details of "a" part 1.50 +0.20 ?.10 +.008 ?004 .059 "a" 0.40(.016) 0.16?.03 (.006?001) 0.145?.055 (.006?002) 0.08(.003) 120-pin plastic lqfp (fpt-120p-m05) (fpt-120p-m13) dimensions in mm (inches) dimensions in mm (inches) 120-pin plastic qfp
134 mb90570 series c 1998 fujitsu limited f120033s-2c-2 1 30 60 31 90 61 120 91 16.00?.10(.630?004)sq 18.00?.20(.709?008)sq 0.50(.020) 0.22?.05 (.009?002) m 0.08(.003) index .006 ?001 +.002 ?.03 +0.05 0.145 "a" 0.08(.003) lead no. .059 ?004 +.008 ?.10 +0.20 1.50 details of "a" part 0~8 (mounting height) 0.45/0.75 (.018/.030) 0.25(.010) (.004?002) 0.10?.05 (stand off) dimensions in mm (inches) 120-pin plastic lqfp (fpt-120p-m21)
136 mb90570 series fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices shinjuku dai-ichi seimei bldg. 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0721, japan tel: +81-3-5322-3347 fax: +81-3-5322-3386 http://edevice.fujitsu.com/ north and south america fujitsu microelectronics, inc. 3545 north first street, san jose, ca 95134-1804, u.s.a. tel: +1-408-922-9000 fax: +1-408-922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: +1-800-866-8608 fax: +1-408-922-9179 http://www.fujitsumicro.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fujitsu-fme.com/ asia pacific fujitsu microelectronics asia pte. ltd. #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-281-0770 fax: +65-281-0220 http://www.fmap.com.sg/ korea fujitsu microelectronics korea ltd. 1702 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 f0101 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the contents of this document may not be reproduced or copied without the permission of fujitsu limited. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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